Hello, I am developing an HLS synthesis tool that outputs VHDL. In this context, I use a little testbench generator to test the generated circuits.
For one of my applications, GHDL fails to compile the testbench an I believe this is an error. It is about this kind of declaration: constant out_vectors_nb : natural := 1; type outvec_type is array (0 to out_vectors_nb-1) of std_logic_vector(out_vector_bytes * 8 - 1 downto 0); constant out_vectors : outvec_type := ( X"00000000" ); When parsing this declaration, GHDL says this: ../vhdl/tb.vhd:74:16: can't match bit string literal "00000000000000000000000000000000" with type array subtype "outvec_type" ghdl: compilation error It seems GHDL doesn't like one-cell array initialization. For any other size, say with out_vectors_nb := 2 or more, and of course a corresponding initialization, GHDL is happy. I believe this is a bug, and indeed in the context of my automatic VHDL generator it is hugely annoying because 1-cell arrays need workaround code to do this. My point also seems correct according to the standard (2000). Am I right/wrong about this? Best regards Adrien Prost-Boucle, Grenoble, France _______________________________________________ Ghdl-discuss mailing list [email protected] https://mail.gna.org/listinfo/ghdl-discuss
