> VHDL-2008 standard support would indeed be great at least for > simulation. For actual synthesis, the issue is the support by > commercial > FPGA vendor tools (amond others). They advertise support of VHDL-93, > sometimes 2002 (and sometimes also a reduced set of constructs from > VHDL > 2008). But the general trend is stick to VHDL-93. > > So I was thinking of a more source-to-source approach: convert > VHDL-2008 > syntax into VHDL-93 (when possible of course). > For that, I was thinking of the Clang approach: Clang is a great > library > for parsing, reformating, ans as front-end/parser for compilation. > > I think it would be great to have something similar for VHDL : build > a > VHDL parser as a general-purpose library, which could be used as > front-end for simulation, conversion to a reasonably structural > representation for input to any synthesis tool, do 2008->93 > reformating > if it's the only possible way etc. > This approach would also de-duplicate some of the work of building > synthesis tools by FPGA vendors. This could be relevant for non-major > FPGA vendors (say others than Xilinx or Altera). > > But I have never written fully compliant VHDL parsers. Some time ago > I > needed to parse of a _very_ reduced set of the syntax so I made a > personal chunk of code to achieve only what I needed but that's all. > Could some GHDL code be reused for that purpose ? > Is it too big to be done ? > > Any thoughts about this ?
There is already some support for that: for example, you can display as vhdl your code after canonization (where concurrent statements are translated to process statements). So, yes GHDL could be used for that purpose (it may require a few adjustments). Note that all 2008 features may not be easily translated to vhdl 93. It could be simpler to create a synthesis tool from GHDL and translate your design to a low-level RTL code. Tristan. _______________________________________________ Ghdl-discuss mailing list [email protected] https://mail.gna.org/listinfo/ghdl-discuss
