On 05/14/2014 01:26 AM, [email protected] wrote:
Hi again :-)
an idea crossed my mind, and I seem to remember that GHDL has some cool
features under the hood, so it might be useful :-)
I'd like to automatically generate a VHDL wrapper for somewhat
arbitrary designs. I can try to parse the top level's entity declaration
but 1) GHDL already parses so why rewrite a parser ?
and 2) the VHDL declaration might contain stuff defined in other files.
This means that I would have to export the interface after elaboration,
while interfacing with the program with some additional code,
but how would I do ? Is VPI a good solution or overkill ?
You wrote something about automatic generations with information of top
entries.
I have I nice idea for simpler writing VHDL code with components.
When I use VHDL files as a component in a Top file, the synchronisation
of signals is a chore.
If you can parse the entries in the files, you can update the component
declaration in package files and the component declaration the higher
hierarchy.
this could be a nice feature.
René Doß
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