Le 2014-07-29 00:41, Patrick Pouget a écrit :
An alternative for the second question:
In general there is a clock genration inside the test. That means there
is a
wait instruction.
By writing something like
Process
If xyz = '0'
Wait 10nS;
Else
Wait;
(some syntax has been omited for clarity)
The simulation quits because there are not more events
I use the same principle, yet with one indirection, in
http://ygdes.com/GHDL/clk/clk_exemple.vhdl
This is less confusing that a "severity failure" :-)
yg
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