Hi Rene, > > In my last email I ask about the possiblity to make some trigger events > to GHDL. I want change vhdl signals from outside. > I get only some short information. But no correct way. > > I had tried this for long time and stopped this. Now some year later I > had found no solution and ask. >
Maybe I don't see your problem, but there's code lying around for years that should do the job, for example whygee's pioneer work (http://ygdes.com/GHDL/). If you want more complex shit with autogenerated HW description and virtual devices, google for ghdlex/netpp. Some folks are also using simple unix pipes for C <-> Simulation I/O, like the classic trick with 'socat' to fake a virtual UART via a PTY. Just found something that should come close, see attachment. You can hack a tad more solutions with socat that can do networking without requiring you to set up your own socket dance. Cheers, - Strubi
-- Simulator <-> C interfacing example via linux pipes -- (c) 2011 Martin Strubel <[email protected]> -- -- -- Under Linux, run this command to create a virtual UART interface -- (replace '<me>' by the user id running the simulation: -- -- > sudo socat PTY,link=/var/run/ghdlsim,raw,echo=0,user=<me> \ -- PTY,link=/var/run/iopipe,raw,echo=0,user=<me> -- -- Then open a terminal on the host side: -- -- > minicom -o -D /var/run/iopipe -- -- and run the simulation: -- ./simpty -- -- What you type into the terminal window is then echoed by the simulation. -- Also, you'll see the characters printed out in hex on the simulation -- windows. library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; -- Unsigned library ghdlex; use ghdlex.ghpi_pipe.all; use ghdlex.txt_util.all; use std.textio.all; entity simpty is end simpty; architecture behaviour of simpty is signal clk : std_ulogic := '0'; signal count : unsigned(7 downto 0) := x"05"; signal data : unsigned(7 downto 0); signal sigterm : std_logic := '0'; signal data_valid : std_logic := '0'; signal pipe_flags : pipeflag_t; -- Pipe handles: shared variable iopipe : pipehandle_t; begin process variable err : integer; begin iopipe := openpipe("/var/run/ghdlsim"); if iopipe < 0 then assert false report "Failed to open PTY pipe" severity failure; end if; clkloop : loop wait for 1 us; clk <= not clk; if sigterm = '1' then exit; end if; end loop clkloop; print(output, " -- TERMINATED --"); closepipe(iopipe); wait; end process; process (clk) variable val : unsigned(7 downto 0); variable inflags : pipeflag_t := "0000"; variable outflags : pipeflag_t := "0000"; begin if rising_edge(clk) then inflags := pipe_flags; pipe_in(iopipe, val, inflags); -- Did we get a byte? if pipe_flags(RX) = '1' then -- Terminate when we get Ctrl-E: if val = x"05" then sigterm <= '1'; end if; data_valid <= '1'; data <= val; print(output, "SIM> " & hstr(val(8-1 downto 0))); -- Loop it back to the sim_touser FIFO: -- FIXME: We don't check for overruns. outflags(TX) := '1'; pipe_out(iopipe, val, outflags); else data_valid <= '0'; end if; -- Save flags for next time pipe_flags <= inflags; end if; end process; end;
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