Hi,
I ran into an issue which I cannot understand. I suspect it could be a bug
in GHDL, of course it even can be that I am not aware of a very trivial
coding issue of mine.
I have two signals:
signal writerClkCntInit : unsigned(1 downto 0) := "00";
signal writerClkCnt: unsigned(1 downto 0) := "00";
At the rising edge of the clock I make an assignment:
report "writerClkCnt <= writerClkCntInit;";
writerClkCnt <= writerClkCntInit;
It is also reflected on the console:
TestFIFO.vhdl:109:24:@1500ns:(report note): rise
TestFIFO.vhdl:78:32:@1500ns:(report note): writerClkCnt <= writerClkCntInit;
In gtkwave, before 1500ns, both signal values are "00". After the
assignment at 1500ns writerClkCnt becomes uninitialized and
writerClkCntInit remains unchanged ("00").
What can cause such anomalies? May I send the files for analysis?
Thanks,
Endre
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