On Fri, 2015-03-27 at 19:46 -0400, Adam Jensen wrote: > In this model, d1 and d2 are essentially the same signal but q1 and q2 behave > differently. (A waveform image is attached). The reset behavior is curious as > well (but that's a bit more subtle).
D1 and D2 are essentially **not** the same signal, this looks exactly as expected to me. D1 and Clk go high at exactly the same time, so on rising_edge(clk) D1 is always '1' therefore q1 is always assigned '1'. D2 is always 1 delta cycle behind D1 so it is always still '0' on rising_edge(clk), with the obvious effect on Q2. If you find a simulator that does anything different, file a bug against it (unless it's a Verilog simulator) -- Brian _______________________________________________ Ghdl-discuss mailing list [email protected] https://mail.gna.org/listinfo/ghdl-discuss
