Hi, I found and installed version 0.33. I used the instruction at: https://sourceforge.net/p/ghdl-updates/code/ci/default/tree/.
When I execute the command: % ghdl --reprint ram_dual_port_sim.vhd I get the following error: ram_dual_port_sim.vhd:38:9: cannot find resource library "unisim" ram_dual_port_sim.vhd:39:12: primary unit "vcomponents" not found in library "unisim" I need to add the libraries to the ghdl library path, I attempted to reference the unisim library using the --work option, but it is not permitted with the --reprint command. I also tried to build portions of ghdl (e.g. make libs.vhdl.gcc and other commands), but I get the following error: "gnatmake -aI./src -aI./src/vhdl -aI./src/psl -aI./src/vhdl/translate -aI./src/ghdldrv \ -gnaty3befhkmr -gnatwae -aO. -gnatf -gnat05 -g -gnata ghdl_gcc -bargs -E -largs gnatmake: "ghdl_gcc" up to date. make -f ./src/ortho/gcc/Makefile \ ortho_srcdir=./src/ortho ortho_exec=ghdl1-gcc \ GNAT_FLAGS="-aI./src -aI./src/vhdl -aI./src/psl -aI./src/vhdl/translate -gnaty3befhkmr -gnatwae -aO. -gnatf -gnat05 -g -gnata" all make[1]: Entering directory `/home/vinny/Desktop/netlist_test/workspace/VHDLParser/ghdl-updates-code' make[1]: *** No rule to make target `/home/vinny/Projects/gcc4.9.2/build/gcc/gtype-vhdl.h', needed by `ortho-lang.o'. Stop. make[1]: Leaving directory `/home/vinny/Desktop/netlist_test/workspace/VHDLParser/ghdl-updates-code' make: *** [ghdl1-gcc] Error 2" I will look into this issue further but, can anyone provide some insight on how to fix this issue? Thanks, On Sat, Jul 11, 2015 at 3:27 PM, Vincent Mirian <[email protected]> wrote: > Hi, > > I tried: > % ghdl --reprint myfile.vhdl > and I got the following error: > ghdl: unknown command '--reprint', try --help > > '--reprint' is not in the description outputted by '--help' nor by > '--options-help'. The version of ghdl that I am using is 0.31. The output > from ghdl --version is: > "GHDL 0.31dev (20132311) [Dunoon edition] > Compiled with GNAT Version: 4.6 > GCC back-end code generator > Written by Tristan Gingold. > > Copyright (C) 2003 - 2010 Tristan Gingold. > GHDL is free software, covered by the GNU General Public License. There > is NO > warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR > PURPOSE." > > I'm suspecting something is wrong with my installation. > > Also, I followed the instructions in the README under the "Compiling for > development.", however I don't believe I did it correctly or my > installation is wrong, since ghdl_gcc is not an executable in the build > directory, but an object file named ghdl_gcc.o. I used the instructions > from: > https://sourceforge.net/p/ghdl-updates/wiki/build%20ghdl%20from%20source%20on%20Linux/. > is there a manner to test my installation? Anything you speculate that > could have gone wrong? > > Any help would be appreciated. Thank you very much for your help, > > On Sat, Jul 11, 2015 at 1:04 AM, Tristan Gingold <[email protected]> wrote: > >> On 11/07/15 04:55, Vincent Mirian wrote: >> >>> Hi, >>> >>> I was able to import the library correctly. The correct commands are: >>> % mkdir unisim >>> % ghdl -i --work=unisim unisim_src/*.vhd >>> >>> When I was trying to import the libraries for primitives on the FPGA. I >>> got an error that 'std_logic_arith' can't be found in library 'ieee'. I >>> used the solution in: >>> >>> http://stackoverflow.com/questions/25837237/is-the-vhdl-package-ieee-std-logic-arith-shipped-with-ghdl >>> . >>> But then, received the error that: >>> >>> - primitive/AFIFO36_INTERNAL.vhd:1391:22: no declaration for >>> "conv_std_logic_vector" >>> >> >> You need to use --ieee=synopsys switch. What is the command line. >> >>> >>> When I attempted to compile the libraries provided by Xilinx in their >>> CAD tool,I get many errors, which I'll need to fix. >>> >> >> No, GHDL can analyze Xilinx libraries without changes. How did you >> try to analyze them ? Please, post the commands you have typed or >> your script. It is difficult to comment without them. >> >> Also, is there a manner for a faster recompile of ghdl. When I make >>> changes to ghdl, and use the build script, It takes a significant amount >>> of time to compile the tool. Is there any flags or settings that I can >>> turn on to increase the speed of the recompile? >>> >> >> There are a few lines for developers in the README file. After a change, >> you just need to build with 'make'. >> >> On another note, I do believe for my end goal, which was mentioned in my >>> previous email, that I do not necessarily need all the libraries from >>> the FPGA vendor. >>> >> >> That's possible but I am not sure this is a good idea. Analyzing Xilinx >> libraries shouldn't be difficult. And without them, you can only work >> on the AST built just after parsing, but without semantic analysis. >> This AST is far from complete. >> >> Ultimately, I would like to know how/where I can gain >>> access to the AST to make the modification I need to the vhdl file and >>> output an equivalent vhdl file with my modifications? >>> >> >> Look at the following procedure in ghdlprint.adb: >> procedure Perform_Action (Cmd : in out Command_Reprint; >> Args : Argument_List) >> >> It reads the files on the command line, analyze them and display >> them using Disp_Vhdl. You can do all you need just before printing >> them. >> >> >> Tristan. >> >> >> _______________________________________________ >> Ghdl-discuss mailing list >> [email protected] >> https://mail.gna.org/listinfo/ghdl-discuss >> > > > > -- > Vincent Mirian > PhD Candidate > Electrical and Computer Engineering > University of Toronto > > Eco-Tip: Save trees! Do you really need to print this email? ;-) > -- Vincent Mirian PhD Candidate Electrical and Computer Engineering University of Toronto Eco-Tip: Save trees! Do you really need to print this email? ;-)
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