The first is how to reply to threads, as I am unable to determine that from the
instructions. In any case, thank you Tristan and Patrick for an unexpectedly
fast response to my previous question.
Now to the more substantial question: I am having trouble determining the
cause of these errors. They are emitted only for the entity decoderNx16, not
decoderNx2. As far as I can tell the two entities have the same syntax. I did
not see any nonprintable characters that were not white space (blanks, tabs,
line feeds) in the file.
$ ghdl -a test.vhdl
test.vhdl:105:22: no declaration for "n"
test.vhdl:105:8: range must be a static discrete range
test.vhdl:107:36: type of prefix is not an array
test.vhdl:109:37: type of prefix is not an array
test.vhdl:110:37: type of prefix is not an array
test.vhdl:111:37: type of prefix is not an array
test.vhdl:112:37: type of prefix is not an array
test.vhdl:113:37: type of prefix is not an array
test.vhdl:114:37: type of prefix is not an array
test.vhdl:115:37: type of prefix is not an array
test.vhdl:116:37: type of prefix is not an array
test.vhdl:117:37: type of prefix is not an array
test.vhdl:118:37: type of prefix is not an array
test.vhdl:119:38: type of prefix is not an array
test.vhdl:120:38: type of prefix is not an array
test.vhdl:121:38: type of prefix is not an array
test.vhdl:122:38: type of prefix is not an array
test.vhdl:123:38: type of prefix is not an array
test.vhdl:124:38: type of prefix is not an array
ghdl: compilation error
$
The contents of test.vhdl are thus, with line numbers added by grep:
1:library ieee;
2:use ieee.std_logic_1164.all;
3:
4:entity decoder1x16 is
5:port(
6: data: in std_logic;
7: y0: out std_logic;
8: y1: out std_logic;
9: y2: out std_logic;
10: y3: out std_logic;
11: y4: out std_logic;
12: y5: out std_logic;
13: y6: out std_logic;
14: y7: out std_logic;
15: y8: out std_logic;
16: y9: out std_logic;
17: y10: out std_logic;
18: y11: out std_logic;
19: y12: out std_logic;
20: y13: out std_logic;
21: y14: out std_logic;
22: y15: out std_logic;
23: address: in std_logic_vector(3 downto 0)
24:);
25:end;
26:
27:architecture struct_decoder1x16 of decoder1x16 is
28:begin
29: with address select y0 <= data when x"0", '0' when others;
30: with address select y1 <= data when x"1", '0' when others;
31: with address select y2 <= data when x"2", '0' when others;
32: with address select y3 <= data when x"3", '0' when others;
33: with address select y4 <= data when x"4", '0' when others;
34: with address select y5 <= data when x"5", '0' when others;
35: with address select y6 <= data when x"6", '0' when others;
36: with address select y7 <= data when x"7", '0' when others;
37: with address select y8 <= data when x"8", '0' when others;
38: with address select y9 <= data when x"9", '0' when others;
39: with address select y10 <= data when x"a", '0' when others;
40: with address select y11 <= data when x"b", '0' when others;
41: with address select y12 <= data when x"c", '0' when others;
42: with address select y13 <= data when x"d", '0' when others;
43: with address select y14 <= data when x"e", '0' when others;
44: with address select y15 <= data when x"f", '0' when others;
45:end;
46:
47:-- For reasons unknown, ghdl appears to ignore the generic definition of N
in this and only
48:-- this architecture. Error messages are generated at line 105 onwards. No
unusual characters
49:-- found in the file where the first error message is generated.
50:
51:library ieee;
52:use ieee.std_logic_1164.all;
53:
54:entity decoderNx16 is
55:generic(
56: N: positive
57:);
58:port(
59: data: in std_logic_vector((N-1) downto 0);
60: address: in std_logic_vector(3 downto 0);
61: y0: out std_logic_vector((N-1) downto 0);
62: y1: out std_logic_vector((N-1) downto 0);
63: y2: out std_logic_vector((N-1) downto 0);
64: y3: out std_logic_vector((N-1) downto 0);
65: y4: out std_logic_vector((N-1) downto 0);
66: y5: out std_logic_vector((N-1) downto 0);
67: y6: out std_logic_vector((N-1) downto 0);
68: y7: out std_logic_vector((N-1) downto 0);
69: y8: out std_logic_vector((N-1) downto 0);
70: y9: out std_logic_vector((N-1) downto 0);
71: y10: out std_logic_vector((N-1) downto 0);
72: y11: out std_logic_vector((N-1) downto 0);
73: y12: out std_logic_vector((N-1) downto 0);
74: y13: out std_logic_vector((N-1) downto 0);
75: y14: out std_logic_vector((N-1) downto 0);
76: y15: out std_logic_vector((N-1) downto 0)
77:);
78:end;
79:
80:architecture struct_decoder1x16 of decoder1x16 is
81:component decoder1x16 is
82:port(
83: data: in std_logic;
84: address: in std_logic_vector(3 downto 0);
85: y0: out std_logic;
86: y1: out std_logic;
87: y2: out std_logic;
88: y3: out std_logic;
89: y4: out std_logic;
90: y5: out std_logic;
91: y6: out std_logic;
92: y7: out std_logic;
93: y8: out std_logic;
94: y9: out std_logic;
95: y10: out std_logic;
96: y11: out std_logic;
97: y12: out std_logic;
98: y13: out std_logic;
99: y14: out std_logic;
100: y15: out std_logic
101:);
102:end component;
103:
104:begin
105: u1: for i in (N-1) downto 0 generate
106: u: decoder1x16 port map(
107: data => data(i),
108: address => address,
109: y0 => y0(i),
110: y1 => y1(i),
111: y2 => y2(i),
112: y3 => y3(i),
113: y4 => y4(i),
114: y5 => y5(i),
115: y6 => y6(i),
116: y7 => y7(i),
117: y8 => y8(i),
118: y9 => y9(i),
119: y10 => y10(i),
120: y11 => y11(i),
121: y12 => y12(i),
122: y13 => y13(i),
123: y14 => y14(i),
124: y15 => y15(i)
125: );
126: end generate u1;
127:end;
128:
129:library ieee;
130:use ieee.std_logic_1164.all;
131:
132:entity decoder1x2 is
133:port(
134: data: in std_logic;
135: selector: in std_logic;
136: y0: out std_logic;
137: y1: out std_logic
138:);
139:end;
140:
141:-- Tested 2015/12/04 with Modelsim. Works.
142:
143:architecture struct_decoder1x2 of decoder1x2 is
144:begin
145: with selector select y0 <= data when '0', '0' when others;
146: with selector select y1 <= data when '1', '0' when others;
147:end;
148:
149:library ieee;
150:use ieee.std_logic_1164.all;
151:
152:entity decoderNx2 is
153:generic(
154: N: positive
155:);
156:port(
157: data: in std_logic_vector((N-1) downto 0);
158: selector: in std_logic;
159: y0: out std_logic_vector((N-1) downto 0);
160: y1: out std_logic_vector((N-1) downto 0)
161:);
162:end;
163:
164:-- tested 2015/12/27 at N = 8 with modelsim. works.
165:
166:architecture struct_decoderNx2 of decoderNx2 is
167:component decoder1x2 is
168:port(
169: data: in std_logic;
170: selector: in std_logic;
171: y0: out std_logic;
172: y1: out std_logic
173:);
174:end component;
175:
176:begin
177: u1: for i in (N-1) downto 0 generate
178: u: decoder1x2 port map(
179: data => data(i),
180: selector => selector,
181: y0 => y0(i),
182: y1 => y1(i)
183: );
184: end generate u1;
185:end;
The obvious question is why GHDL is complaining about decoderNx16 and not
decoderNx2.
Cheers
John
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