Re: [Ghdl-discuss] GHDL as "real" simulator

[Christiano SA]

Hi, I do not know much about programming in linux environment and VHDL but I have similar interest like you.

I've attached an example.

 

To run:

$ ghdl -a a.vhdl b.vhdl main.vhdl

$ gcc -c f.c
$ ghdl -e -Wl,f.o main
$ ./main

Hi
Hi

Hi
Hi

Hi
Hi

(...)

 

In this program, the a.vhdl call a C function and sleep for 1 second, after return to a.vdhl it negate clk to which b.vhdl is sensitive and reacts writting "Hi" on screen.

 

Have you worked with PySerial (a python library)? In PySerial you can call a function which sleep until receive a serial message and then return to the program.

Like this:

>>> ser = serial.Serial('/dev/ttyUSB0', 1200)
>>> s = ser.read(100)       # Wait to read up to one hundred bytes

If you do a C function like this you can do the VHDL entity sleep until receive what you want, the same thing to network messages.

Although I have not tested for not being expert in VHDL, I believe it is also possible to write a function within the VHDL and pass the address of this function to a C function, it would be interesting because most of the libraries use handlers to events. If anyone has tested this I would like to know.

 

References:

http://ghdl.readthedocs.io/en/latest/GHDL_implementation_of_VHDL.html#interfacing-to-other-languages

http://ygdes.com/GHDL/

 

Sent: Friday, June 03, 2016 at 5:52 AM
From: "Vít Fábera" <fab...@fd.cvut.cz>
To: ghdl-discuss@gna.org
Subject: [Ghdl-discuss] GHDL as "real" simulator

Hello,

we would like to use GHDL as simulator as real simulator.
it means simulate FSMs with real input and set real outputs.

We would like to create library with commands like writeline,
which would send data for example to serial port, to network
via UDP/TCP packet and, naturaly, with function like read.

Does anybody create such library or similar extension of GHDL?


Thean you for answer


Vit Fabera
Faculty of Transportation Sciences
Czech Technical University

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library ieee;
use ieee.std_logic_1164.all;

package pac_a is

  procedure fxch;
    attribute foreign of fxch:
    procedure is "VHPIDIRECT fxch";
  
end pac_a;

package body pac_a is

  procedure fxch is
  begin
    assert false report "VHPI" severity failure;
  end fxch;
    

end pac_a;


library ieee;
use ieee.std_logic_1164.all;
library work;
use work.pac_a.all;

entity a is
  port(
    clk : inout std_ulogic:='0'
  );
end entity;

architecture simple_a of a is
begin
  process is
  begin
      wait for 0 us;
      fxch;
      clk <= not clk;

  end process;
end simple_a;

library std; use std.textio.all;
library ieee;
use ieee.std_logic_1164.all;

entity b is
  port(i0: in std_ulogic);
end b;

architecture test_b of b is
begin
  process
    variable x1: line;
  begin
    wait until rising_edge(i0);
    write(x1, String'("Hi"));
    writeline(output, x1);
  end process;
end test_b;

void fxch()
{
  usleep(1000000);
}



library std; use std.textio.all;
library ieee;
use ieee.std_logic_1164.all;
library work;

entity main is
 
end main;

architecture test of main is
  signal m0 : std_ulogic:='0';
begin

 A : entity work.a
   port map(m0);

 B : entity work.b
   port map(m0);
  
end test;

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