On 12/06/16 15:46, Walter F.J. Mueller wrote:
Hi *,
in the FOSDEM16 ghdl slides
https://fosdem.org/2016/schedule/event/ghdl/attachments/slides/940/export/events/attachments/ghdl/slides/940/FOSDEM16_ghdl.pdf
I see some statements on 'Multi language simulation'
The target seems to be VHDL + SystemC. There are the lines
* And not Verilog ?
* SystemC is simpler
Might be that SystemC is simpler to integrate.
However:
* Verilog is certainly more relevant !!
* Many device models are only available in Verilog
* EDA Tools these days simply expect that the simulator
is 'mixed langauge', so generated files are often only
in Verilog. And if there is VHDL, it's by far not as
well maintained than Verilog.
Note that this was a proof of concept, not a full integration.
I'm not aware of an open source VHDL+Verilog simulator.
If ghdl goes in this direction it be great.
There is a project to combine icarus verilog and ghdl: mhdlsim.
Tristan.
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