tree b3d41af3d79fee4ae1c617a6da596202709fd2d5
parent d6b0bf213b4be478029b768fcee80058ace7150a
author Ben Dooks <[EMAIL PROTECTED]> Mon, 29 Aug 2005 22:46:31 +0100
committer Russell King <[EMAIL PROTECTED]> Mon, 29 Aug 2005 22:46:31 +0100
[ARM] 2856/1: S3C2440 - show DVS status at startup
Patch from Ben Dooks
Show the state of DVS (Dynamic Voltage Scaling) when
starting up on the S3C2440
Signed-off-by: Ben Dooks <[EMAIL PROTECTED]>
Signed-off-by: Russell King <[EMAIL PROTECTED]>
arch/arm/mach-s3c2410/s3c2440-clock.c | 6 ++++--
1 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-s3c2410/s3c2440-clock.c
b/arch/arm/mach-s3c2410/s3c2440-clock.c
--- a/arch/arm/mach-s3c2410/s3c2440-clock.c
+++ b/arch/arm/mach-s3c2410/s3c2440-clock.c
@@ -68,6 +68,7 @@ static struct clk s3c2440_clk_ac97 = {
static int s3c2440_clk_add(struct sys_device *sysdev)
{
unsigned long upllcon = __raw_readl(S3C2410_UPLLCON);
+ unsigned long camdivn = __raw_readl(S3C2440_CAMDIVN);
struct clk *clk_h;
struct clk *clk_p;
struct clk *clk_xtal;
@@ -80,8 +81,9 @@ static int s3c2440_clk_add(struct sys_de
s3c2440_clk_upll.rate = s3c2410_get_pll(upllcon, clk_xtal->rate);
- printk("S3C2440: Clock Support, UPLL %ld.%03ld MHz\n",
- print_mhz(s3c2440_clk_upll.rate));
+ printk("S3C2440: Clock Support, UPLL %ld.%03ld MHz, DVS %s\n",
+ print_mhz(s3c2440_clk_upll.rate),
+ (camdivn & S3C2440_CAMDIVN_DVSEN) ? "on" : "off");
clk_p = clk_get(NULL, "pclk");
clk_h = clk_get(NULL, "hclk");
-
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