Gitweb:     
http://git.kernel.org/git/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commit;h=3ea163e44c041b9e1d7314998dfbfd4fbc6eea20
Commit:     3ea163e44c041b9e1d7314998dfbfd4fbc6eea20
Parent:     9b938166907558e664d8fa413e6233a36669e0c0
Author:     Andrew Victor <[EMAIL PROTECTED]>
AuthorDate: Tue Jan 9 13:47:29 2007 +0100
Committer:  Russell King <[EMAIL PROTECTED]>
CommitDate: Wed Jan 24 11:59:56 2007 +0000

    [ARM] 4089/1: AT91: GPIO wake IRQ cleanup
    
    Cleanup of at91 platform level gpio wake and suspend/resume logic.
    
    The GPIO core now delegates wakeups to the parent AIC by refcounting,
    and delegates clock management to the clock API.  This makes these
    system modules more independent of each other, which is cleaner and will
    also help with the AT91SAM9263 (where some GPIO controllers share the
    same irq and clock).
    
    Original patch by David Brownell.
    
    Signed-off-by: Andrew Victor <[EMAIL PROTECTED]>
    Signed-off-by: Russell King <[EMAIL PROTECTED]>
---
 arch/arm/mach-at91rm9200/gpio.c |   39 +++++++++++++--------------------------
 1 files changed, 13 insertions(+), 26 deletions(-)

diff --git a/arch/arm/mach-at91rm9200/gpio.c b/arch/arm/mach-at91rm9200/gpio.c
index 3f18850..af22659 100644
--- a/arch/arm/mach-at91rm9200/gpio.c
+++ b/arch/arm/mach-at91rm9200/gpio.c
@@ -20,7 +20,6 @@
 #include <asm/io.h>
 #include <asm/hardware.h>
 #include <asm/arch/at91_pio.h>
-#include <asm/arch/at91_pmc.h>
 #include <asm/arch/gpio.h>
 
 #include "generic.h"
@@ -224,17 +223,17 @@ static u32 backups[MAX_GPIO_BANKS];
 static int gpio_irq_set_wake(unsigned pin, unsigned state)
 {
        unsigned        mask = pin_to_mask(pin);
+       unsigned        bank = (pin - PIN_BASE) / 32;
 
-       pin -= PIN_BASE;
-       pin /= 32;
-
-       if (unlikely(pin >= MAX_GPIO_BANKS))
+       if (unlikely(bank >= MAX_GPIO_BANKS))
                return -EINVAL;
 
        if (state)
-               wakeups[pin] |= mask;
+               wakeups[bank] |= mask;
        else
-               wakeups[pin] &= ~mask;
+               wakeups[bank] &= ~mask;
+
+       set_irq_wake(gpio[bank].id, state);
 
        return 0;
 }
@@ -246,29 +245,15 @@ void at91_gpio_suspend(void)
        for (i = 0; i < gpio_banks; i++) {
                u32 pio = gpio[i].offset;
 
-               /*
-                * Note: drivers should have disabled GPIO interrupts that
-                * aren't supposed to be wakeup sources.
-                * But that is not much good on ARM.....  disable_irq() does
-                * not update the hardware immediately, so the hardware mask
-                * (IMR) has the wrong value (not current, too much is
-                * permitted).
-                *
-                * Our workaround is to disable all non-wakeup IRQs ...
-                * which is exactly what correct drivers asked for in the
-                * first place!
-                */
                backups[i] = at91_sys_read(pio + PIO_IMR);
                at91_sys_write(pio + PIO_IDR, backups[i]);
                at91_sys_write(pio + PIO_IER, wakeups[i]);
 
-               if (!wakeups[i]) {
-                       disable_irq_wake(gpio[i].id);
-                       at91_sys_write(AT91_PMC_PCDR, 1 << gpio[i].id);
-               } else {
-                       enable_irq_wake(gpio[i].id);
+               if (!wakeups[i])
+                       clk_disable(gpio[i].clock);
+               else {
 #ifdef CONFIG_PM_DEBUG
-                       printk(KERN_DEBUG "GPIO-%c may wake for %08x\n", 
"ABCD"[i], wakeups[i]);
+                       printk(KERN_DEBUG "GPIO-%c may wake for %08x\n", 'A'+i, 
wakeups[i]);
 #endif
                }
        }
@@ -281,9 +266,11 @@ void at91_gpio_resume(void)
        for (i = 0; i < gpio_banks; i++) {
                u32 pio = gpio[i].offset;
 
+               if (!wakeups[i])
+                       clk_enable(gpio[i].clock);
+
                at91_sys_write(pio + PIO_IDR, wakeups[i]);
                at91_sys_write(pio + PIO_IER, backups[i]);
-               at91_sys_write(AT91_PMC_PCER, 1 << gpio[i].id);
        }
 }
 
-
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