Gitweb:     
http://git.kernel.org/git/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commit;h=7baced8a5923ce13d3d42d50a042a869092ab4e5
Commit:     7baced8a5923ce13d3d42d50a042a869092ab4e5
Parent:     d4e1c889c1ec547371227558e1da5f2f50c7dd5e
Author:     Matt Reimer <[EMAIL PROTECTED]>
AuthorDate: Wed Jan 24 01:30:37 2007 +0100
Committer:  Russell King <[EMAIL PROTECTED]>
CommitDate: Wed Jan 24 12:04:17 2007 +0000

    [ARM] 4106/1: S3C2410: typo fixes in register definitions
    
    The Trcd* bits of the S3C24xx BANKCON6 and BANKCON7 registers are 
misspelled in include/asm-arm/arch-s3c2410/regs-mem.h as Trdc*.
    
    Signed-off-by: Matt Reimer <[EMAIL PROTECTED]>
    Acked-by: Ben Dooks <[EMAIL PROTECTED]>
    Signed-off-by: Russell King <[EMAIL PROTECTED]>
---
 include/asm-arm/arch-s3c2410/regs-mem.h |   14 +++++++-------
 1 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/include/asm-arm/arch-s3c2410/regs-mem.h 
b/include/asm-arm/arch-s3c2410/regs-mem.h
index 375dca5..e4d8234 100644
--- a/include/asm-arm/arch-s3c2410/regs-mem.h
+++ b/include/asm-arm/arch-s3c2410/regs-mem.h
@@ -133,10 +133,10 @@
 #define S3C2410_BANKCON_SDRAM          (0x3 << 15)
 
 /* next bits only for EDO DRAM in 6,7 */
-#define S3C2400_BANKCON_EDO_Trdc1      (0x00 << 4)
-#define S3C2400_BANKCON_EDO_Trdc2      (0x01 << 4)
-#define S3C2400_BANKCON_EDO_Trdc3      (0x02 << 4)
-#define S3C2400_BANKCON_EDO_Trdc4      (0x03 << 4)
+#define S3C2400_BANKCON_EDO_Trcd1      (0x00 << 4)
+#define S3C2400_BANKCON_EDO_Trcd2      (0x01 << 4)
+#define S3C2400_BANKCON_EDO_Trcd3      (0x02 << 4)
+#define S3C2400_BANKCON_EDO_Trcd4      (0x03 << 4)
 
 /* CAS pulse width */
 #define S3C2400_BANKCON_EDO_PULSE1     (0x00 << 3)
@@ -153,9 +153,9 @@
 #define S3C2400_BANKCON_EDO_SCANb11    (0x03 << 0)
 
 /* next bits only for SDRAM in 6,7 */
-#define S3C2410_BANKCON_Trdc2          (0x00 << 2)
-#define S3C2410_BANKCON_Trdc3          (0x01 << 2)
-#define S3C2410_BANKCON_Trdc4          (0x02 << 2)
+#define S3C2410_BANKCON_Trcd2          (0x00 << 2)
+#define S3C2410_BANKCON_Trcd3          (0x01 << 2)
+#define S3C2410_BANKCON_Trcd4          (0x02 << 2)
 
 /* control column address select */
 #define S3C2410_BANKCON_SCANb8         (0x00 << 0)
-
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