Gitweb:     
http://git.kernel.org/git/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commit;h=9918cda52368ec3df5bb6bc1630ba8c070ad9fdd
Commit:     9918cda52368ec3df5bb6bc1630ba8c070ad9fdd
Parent:     ae0a846e411dc0b568e8ccda584896310ee5f369
Author:     Uwe Kleine-König <[EMAIL PROTECTED]>
AuthorDate: Fri Feb 16 15:36:55 2007 +0100
Committer:  Russell King <[EMAIL PROTECTED]>
CommitDate: Sat Feb 17 20:05:45 2007 +0000

    [ARM] 4210/1: base for new machine type "NetSilicon NS9360"
    
    Signed-off-by: Uwe Kleine-König <[EMAIL PROTECTED]>
    Signed-off-by: Russell King <[EMAIL PROTECTED]>
---
 arch/arm/Kconfig                                   |   10 +
 arch/arm/Makefile                                  |   10 +-
 arch/arm/mach-ns9xxx/Kconfig                       |   21 ++
 arch/arm/mach-ns9xxx/Makefile                      |    5 +
 arch/arm/mach-ns9xxx/Makefile.boot                 |    2 +
 arch/arm/mach-ns9xxx/board-a9m9750dev.c            |  199 ++++++++++++++++++++
 arch/arm/mach-ns9xxx/board-a9m9750dev.h            |   15 ++
 arch/arm/mach-ns9xxx/generic.c                     |   42 ++++
 arch/arm/mach-ns9xxx/generic.h                     |   19 ++
 arch/arm/mach-ns9xxx/irq.c                         |   94 +++++++++
 arch/arm/mach-ns9xxx/mach-cc9p9360dev.c            |   41 ++++
 arch/arm/mach-ns9xxx/time.c                        |   88 +++++++++
 arch/arm/mm/Kconfig                                |    4 +-
 include/asm-arm/arch-ns9xxx/board.h                |   18 ++
 include/asm-arm/arch-ns9xxx/clock.h                |   37 ++++
 include/asm-arm/arch-ns9xxx/debug-macro.S          |   22 +++
 include/asm-arm/arch-ns9xxx/dma.h                  |   14 ++
 include/asm-arm/arch-ns9xxx/entry-macro.S          |   22 +++
 include/asm-arm/arch-ns9xxx/hardware.h             |   67 +++++++
 include/asm-arm/arch-ns9xxx/io.h                   |   20 ++
 include/asm-arm/arch-ns9xxx/irqs.h                 |   85 +++++++++
 include/asm-arm/arch-ns9xxx/memory.h               |   27 +++
 include/asm-arm/arch-ns9xxx/processor.h            |   18 ++
 include/asm-arm/arch-ns9xxx/regs-bbu.h             |   21 ++
 .../asm-arm/arch-ns9xxx/regs-board-a9m9750dev.h    |   24 +++
 include/asm-arm/arch-ns9xxx/regs-mem.h             |  135 +++++++++++++
 include/asm-arm/arch-ns9xxx/regs-sys.h             |  157 +++++++++++++++
 include/asm-arm/arch-ns9xxx/system.h               |   34 ++++
 include/asm-arm/arch-ns9xxx/timex.h                |   20 ++
 include/asm-arm/arch-ns9xxx/uncompress.h           |   35 ++++
 include/asm-arm/arch-ns9xxx/vmalloc.h              |   16 ++
 31 files changed, 1316 insertions(+), 6 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 6783c2e..c843508 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -271,6 +271,14 @@ config ARCH_L7200
          If you have any questions or comments about the Linux kernel port
          to this board, send e-mail to <[EMAIL PROTECTED]>.
 
+config ARCH_NS9XXX
+       bool "NetSilicon NS9xxx"
+       help
+         Say Y here if you intend to run this kernel on a NetSilicon NS9xxx
+         System.
+
+         <http://www.digi.com/products/microprocessors/index.jsp>
+
 config ARCH_PNX4008
        bool "Philips Nexperia PNX4008 Mobile"
        help
@@ -381,6 +389,8 @@ source "arch/arm/mach-at91rm9200/Kconfig"
 
 source "arch/arm/mach-netx/Kconfig"
 
+source "arch/arm/mach-ns9xxx/Kconfig"
+
 # Definitions to make life easier
 config ARCH_ACORN
        bool
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 000f110..52d1194 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -124,10 +124,12 @@ endif
  machine-$(CONFIG_ARCH_H720X)     := h720x
  machine-$(CONFIG_ARCH_AAEC2000)   := aaec2000
  machine-$(CONFIG_ARCH_REALVIEW)   := realview
- machine-$(CONFIG_ARCH_AT91)       := at91rm9200
- machine-$(CONFIG_ARCH_EP93XX)     := ep93xx
- machine-$(CONFIG_ARCH_PNX4008)    := pnx4008
- machine-$(CONFIG_ARCH_NETX)       := netx
+ machine-$(CONFIG_ARCH_AT91)      := at91rm9200
+ machine-$(CONFIG_ARCH_EP93XX)    := ep93xx
+ machine-$(CONFIG_ARCH_PNX4008)           := pnx4008
+ machine-$(CONFIG_ARCH_NETX)      := netx
+ machine-$(CONFIG_ARCH_NS9XXX)    := ns9xxx
+ textofs-$(CONFIG_ARCH_NS9XXX)    := 0x00108000
 
 ifeq ($(CONFIG_ARCH_EBSA110),y)
 # This is what happens if you forget the IOCS16 line.
diff --git a/arch/arm/mach-ns9xxx/Kconfig b/arch/arm/mach-ns9xxx/Kconfig
new file mode 100644
index 0000000..8175ba9
--- /dev/null
+++ b/arch/arm/mach-ns9xxx/Kconfig
@@ -0,0 +1,21 @@
+if ARCH_NS9XXX
+
+menu "NS9xxx Implementations"
+
+config MACH_CC9P9360DEV
+       bool "Connect Core 9P 9360 on an A9M9750 Devboard"
+       select PROCESSOR_NS9360
+       select BOARD_A9M9750DEV
+       help
+         Say Y here if you are using the Digi Connect Core 9P 9360
+         on an A9M9750 Development Board.
+
+config PROCESSOR_NS9360
+       bool
+
+config BOARD_A9M9750DEV
+       bool
+
+endmenu
+
+endif
diff --git a/arch/arm/mach-ns9xxx/Makefile b/arch/arm/mach-ns9xxx/Makefile
new file mode 100644
index 0000000..91e945f
--- /dev/null
+++ b/arch/arm/mach-ns9xxx/Makefile
@@ -0,0 +1,5 @@
+obj-y := irq.o time.o generic.o
+
+obj-$(CONFIG_MACH_CC9P9360DEV) += mach-cc9p9360dev.o
+
+obj-$(CONFIG_BOARD_A9M9750DEV) += board-a9m9750dev.o
diff --git a/arch/arm/mach-ns9xxx/Makefile.boot 
b/arch/arm/mach-ns9xxx/Makefile.boot
new file mode 100644
index 0000000..75ed64e
--- /dev/null
+++ b/arch/arm/mach-ns9xxx/Makefile.boot
@@ -0,0 +1,2 @@
+zreladdr-y := 0x108000
+params_phys-y := 0x100
diff --git a/arch/arm/mach-ns9xxx/board-a9m9750dev.c 
b/arch/arm/mach-ns9xxx/board-a9m9750dev.c
new file mode 100644
index 0000000..2528988
--- /dev/null
+++ b/arch/arm/mach-ns9xxx/board-a9m9750dev.c
@@ -0,0 +1,199 @@
+/*
+ * arch/arm/mach-ns9xxx/board-a9m9750dev.c
+ *
+ * Copyright (C) 2006,2007 by Digi International Inc.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ */
+#include <linux/platform_device.h>
+#include <linux/serial_8250.h>
+#include <linux/irq.h>
+
+#include <asm/mach/map.h>
+
+#include <asm/arch-ns9xxx/board.h>
+#include <asm/arch-ns9xxx/regs-sys.h>
+#include <asm/arch-ns9xxx/regs-mem.h>
+#include <asm/arch-ns9xxx/regs-bbu.h>
+#include <asm/arch-ns9xxx/regs-board-a9m9750dev.h>
+
+#include "board-a9m9750dev.h"
+
+static struct map_desc board_a9m9750dev_io_desc[] __initdata = {
+       { /* FPGA on CS0 */
+               .virtual = io_p2v(NS9XXX_CSxSTAT_PHYS(0)),
+               .pfn = __phys_to_pfn(NS9XXX_CSxSTAT_PHYS(0)),
+               .length = NS9XXX_CS0STAT_LENGTH,
+               .type = MT_DEVICE,
+       },
+};
+
+void __init board_a9m9750dev_map_io(void)
+{
+       iotable_init(board_a9m9750dev_io_desc,
+                    ARRAY_SIZE(board_a9m9750dev_io_desc));
+}
+
+static void a9m9750dev_fpga_ack_irq(unsigned int irq)
+{
+       /* nothing */
+}
+
+static void a9m9750dev_fpga_mask_irq(unsigned int irq)
+{
+       FPGA_IER &= ~(1 << (irq - FPGA_IRQ(0)));
+}
+
+static void a9m9750dev_fpga_maskack_irq(unsigned int irq)
+{
+       a9m9750dev_fpga_mask_irq(irq);
+       a9m9750dev_fpga_ack_irq(irq);
+}
+
+static void a9m9750dev_fpga_unmask_irq(unsigned int irq)
+{
+       FPGA_IER |= 1 << (irq - FPGA_IRQ(0));
+}
+
+static struct irq_chip a9m9750dev_fpga_chip = {
+       .ack            = a9m9750dev_fpga_ack_irq,
+       .mask           = a9m9750dev_fpga_mask_irq,
+       .mask_ack       = a9m9750dev_fpga_maskack_irq,
+       .unmask         = a9m9750dev_fpga_unmask_irq,
+};
+
+static void a9m9750dev_fpga_demux_handler(unsigned int irq,
+               struct irq_desc *desc)
+{
+       int stat = FPGA_ISR;
+
+       while (stat != 0) {
+               int irqno = fls(stat) - 1;
+
+               stat &= ~(1 << irqno);
+
+               desc = irq_desc + FPGA_IRQ(irqno);
+
+               desc_handle_irq(irqno, desc);
+       }
+}
+
+void __init board_a9m9750dev_init_irq(void)
+{
+       u32 reg;
+       int i;
+
+       /*
+        * configure gpio for IRQ_EXT2
+        * use GPIO 11, because GPIO 32 is used for the LCD
+        */
+       /* XXX: proper GPIO handling */
+       BBU_GC(2) &= ~0x2000;
+
+       for (i = FPGA_IRQ(0); i <= FPGA_IRQ(7); ++i) {
+               set_irq_chip(i, &a9m9750dev_fpga_chip);
+               set_irq_handler(i, handle_level_irq);
+               set_irq_flags(i, IRQF_VALID);
+       }
+
+       /* IRQ_EXT2: level sensitive + active low */
+       reg = SYS_EIC(2);
+       REGSET(reg, SYS_EIC, PLTY, AL);
+       REGSET(reg, SYS_EIC, LVEDG, LEVEL);
+       SYS_EIC(2) = reg;
+
+       set_irq_chained_handler(IRQ_EXT2,
+                       a9m9750dev_fpga_demux_handler);
+}
+
+static struct plat_serial8250_port board_a9m9750dev_serial8250_port[] = {
+       {
+               .iobase         = FPGA_UARTA_BASE,
+               .membase        = (unsigned char*)FPGA_UARTA_BASE,
+               .mapbase        = FPGA_UARTA_BASE,
+               .irq            = IRQ_FPGA_UARTA,
+               .iotype         = UPIO_MEM,
+               .uartclk        = 18432000,
+               .regshift       = 0,
+               .flags          = UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ,
+       }, {
+               .iobase         = FPGA_UARTB_BASE,
+               .membase        = (unsigned char*)FPGA_UARTB_BASE,
+               .mapbase        = FPGA_UARTB_BASE,
+               .irq            = IRQ_FPGA_UARTB,
+               .iotype         = UPIO_MEM,
+               .uartclk        = 18432000,
+               .regshift       = 0,
+               .flags          = UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ,
+       }, {
+               .iobase         = FPGA_UARTC_BASE,
+               .membase        = (unsigned char*)FPGA_UARTC_BASE,
+               .mapbase        = FPGA_UARTC_BASE,
+               .irq            = IRQ_FPGA_UARTC,
+               .iotype         = UPIO_MEM,
+               .uartclk        = 18432000,
+               .regshift       = 0,
+               .flags          = UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ,
+       }, {
+               .iobase         = FPGA_UARTD_BASE,
+               .membase        = (unsigned char*)FPGA_UARTD_BASE,
+               .mapbase        = FPGA_UARTD_BASE,
+               .irq            = IRQ_FPGA_UARTD,
+               .iotype         = UPIO_MEM,
+               .uartclk        = 18432000,
+               .regshift       = 0,
+               .flags          = UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ,
+       }, {
+               /* end marker */
+       },
+};
+
+static struct platform_device board_a9m9750dev_serial_device = {
+       .name = "serial8250",
+       .dev = {
+               .platform_data = board_a9m9750dev_serial8250_port,
+       },
+};
+
+static struct platform_device *board_a9m9750dev_devices[] __initdata = {
+       &board_a9m9750dev_serial_device,
+};
+
+void __init board_a9m9750dev_init_machine(void)
+{
+       u32 reg;
+
+       /* setup static CS0: memory base ... */
+       REGSETIM(SYS_SMCSSMB(0), SYS_SMCSSMB, CSxB,
+                       NS9XXX_CSxSTAT_PHYS(0) >> 12);
+
+       /* ... and mask */
+       reg = SYS_SMCSSMM(0);
+       REGSETIM(reg, SYS_SMCSSMM, CSxM, 0xfffff);
+       REGSET(reg, SYS_SMCSSMM, CSEx, EN);
+       SYS_SMCSSMM(0) = reg;
+
+       /* setup static CS0: memory configuration */
+       reg = MEM_SMC(0);
+       REGSET(reg, MEM_SMC, WSMC, OFF);
+       REGSET(reg, MEM_SMC, BSMC, OFF);
+       REGSET(reg, MEM_SMC, EW, OFF);
+       REGSET(reg, MEM_SMC, PB, 1);
+       REGSET(reg, MEM_SMC, PC, AL);
+       REGSET(reg, MEM_SMC, PM, DIS);
+       REGSET(reg, MEM_SMC, MW, 8);
+       MEM_SMC(0) = reg;
+
+       /* setup static CS0: timing */
+       MEM_SMWED(0) = 0x2;
+       MEM_SMOED(0) = 0x2;
+       MEM_SMRD(0) = 0x6;
+       MEM_SMWD(0) = 0x6;
+
+       platform_add_devices(board_a9m9750dev_devices,
+                       ARRAY_SIZE(board_a9m9750dev_devices));
+}
+
diff --git a/arch/arm/mach-ns9xxx/board-a9m9750dev.h 
b/arch/arm/mach-ns9xxx/board-a9m9750dev.h
new file mode 100644
index 0000000..edc75ab
--- /dev/null
+++ b/arch/arm/mach-ns9xxx/board-a9m9750dev.h
@@ -0,0 +1,15 @@
+/*
+ * arch/arm/mach-ns9xxx/board-a9m9750dev.h
+ *
+ * Copyright (C) 2006 by Digi International Inc.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ */
+#include <linux/init.h>
+
+void __init board_a9m9750dev_map_io(void);
+void __init board_a9m9750dev_init_machine(void);
+void __init board_a9m9750dev_init_irq(void);
diff --git a/arch/arm/mach-ns9xxx/generic.c b/arch/arm/mach-ns9xxx/generic.c
new file mode 100644
index 0000000..83e2b65
--- /dev/null
+++ b/arch/arm/mach-ns9xxx/generic.c
@@ -0,0 +1,42 @@
+/*
+ * arch/arm/mach-ns9xxx/generic.c
+ *
+ * Copyright (C) 2006 by Digi International Inc.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <asm/memory.h>
+#include <asm/page.h>
+#include <asm/mach-types.h>
+#include <asm/mach/map.h>
+#include <asm/arch-ns9xxx/regs-sys.h>
+#include <asm/arch-ns9xxx/regs-mem.h>
+#include <asm/arch-ns9xxx/board.h>
+
+static struct map_desc standard_io_desc[] __initdata = {
+       { /* BBus */
+               .virtual = io_p2v(0x90000000),
+               .pfn = __phys_to_pfn(0x90000000),
+               .length = 0x00700000,
+               .type = MT_DEVICE,
+       }, { /* AHB */
+               .virtual = io_p2v(0xa0100000),
+               .pfn = __phys_to_pfn(0xa0100000),
+               .length = 0x00900000,
+               .type = MT_DEVICE,
+       },
+};
+
+void __init ns9xxx_map_io(void)
+{
+       iotable_init(standard_io_desc, ARRAY_SIZE(standard_io_desc));
+}
+
+void __init ns9xxx_init_machine(void)
+{
+}
diff --git a/arch/arm/mach-ns9xxx/generic.h b/arch/arm/mach-ns9xxx/generic.h
new file mode 100644
index 0000000..687e291
--- /dev/null
+++ b/arch/arm/mach-ns9xxx/generic.h
@@ -0,0 +1,19 @@
+/*
+ * arch/arm/mach-ns9xxx/generic.h
+ *
+ * Copyright (C) 2006 by Digi International Inc.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ */
+#include <linux/time.h>
+#include <asm/mach/time.h>
+#include <linux/init.h>
+
+void __init ns9xxx_init_irq(void);
+void __init ns9xxx_map_io(void);
+void __init ns9xxx_init_machine(void);
+
+extern struct sys_timer ns9xxx_timer;
diff --git a/arch/arm/mach-ns9xxx/irq.c b/arch/arm/mach-ns9xxx/irq.c
new file mode 100644
index 0000000..83d9272
--- /dev/null
+++ b/arch/arm/mach-ns9xxx/irq.c
@@ -0,0 +1,94 @@
+/*
+ * arch/arm/mach-ns9xxx/irq.c
+ *
+ * Copyright (C) 2006,2007 by Digi International Inc.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ */
+#include <linux/interrupt.h>
+#include <asm/mach/irq.h>
+#include <asm/mach-types.h>
+#include <asm/arch-ns9xxx/regs-sys.h>
+#include <asm/arch-ns9xxx/irqs.h>
+#include <asm/arch-ns9xxx/board.h>
+
+#include "generic.h"
+
+static void ns9xxx_ack_irq_timer(unsigned int irq)
+{
+       u32 tc = SYS_TC(irq - IRQ_TIMER0);
+
+       REGSET(tc, SYS_TCx, INTC, SET);
+       SYS_TC(irq - IRQ_TIMER0) = tc;
+
+       REGSET(tc, SYS_TCx, INTC, UNSET);
+       SYS_TC(irq - IRQ_TIMER0) = tc;
+}
+
+void (*ns9xxx_ack_irq_functions[NR_IRQS])(unsigned int) = {
+       [IRQ_TIMER0] = ns9xxx_ack_irq_timer,
+       [IRQ_TIMER1] = ns9xxx_ack_irq_timer,
+       [IRQ_TIMER2] = ns9xxx_ack_irq_timer,
+       [IRQ_TIMER3] = ns9xxx_ack_irq_timer,
+};
+
+static void ns9xxx_mask_irq(unsigned int irq)
+{
+       /* XXX: better use cpp symbols */
+       SYS_IC(irq / 4) &= ~(1 << (7 + 8 * (3 - (irq & 3))));
+}
+
+static void ns9xxx_ack_irq(unsigned int irq)
+{
+       if (!ns9xxx_ack_irq_functions[irq]) {
+               printk(KERN_ERR "no ack function for irq %u\n", irq);
+               BUG();
+       }
+
+       ns9xxx_ack_irq_functions[irq](irq);
+       SYS_ISRADDR = 0;
+}
+
+static void ns9xxx_maskack_irq(unsigned int irq)
+{
+       ns9xxx_mask_irq(irq);
+       ns9xxx_ack_irq(irq);
+}
+
+static void ns9xxx_unmask_irq(unsigned int irq)
+{
+       /* XXX: better use cpp symbols */
+       SYS_IC(irq / 4) |= 1 << (7 + 8 * (3 - (irq & 3)));
+}
+
+static struct irq_chip ns9xxx_chip = {
+       .ack            = ns9xxx_ack_irq,
+       .mask           = ns9xxx_mask_irq,
+       .mask_ack       = ns9xxx_maskack_irq,
+       .unmask         = ns9xxx_unmask_irq,
+};
+
+void __init ns9xxx_init_irq(void)
+{
+       int i;
+
+       /* disable all IRQs */
+       for (i = 0; i < 8; ++i)
+               SYS_IC(i) = (4 * i) << 24 | (4 * i + 1) << 16 |
+                       (4 * i + 2) << 8 | (4 * i + 3);
+
+       /* simple interrupt prio table:
+        * prio(x) < prio(y) <=> x < y
+        */
+       for (i = 0; i < 32; ++i)
+               SYS_IVA(i) = i;
+
+       for (i = IRQ_WATCHDOG; i <= IRQ_EXT3; ++i) {
+               set_irq_chip(i, &ns9xxx_chip);
+               set_irq_handler(i, handle_level_irq);
+               set_irq_flags(i, IRQF_VALID);
+       }
+}
diff --git a/arch/arm/mach-ns9xxx/mach-cc9p9360dev.c 
b/arch/arm/mach-ns9xxx/mach-cc9p9360dev.c
new file mode 100644
index 0000000..a193dd9
--- /dev/null
+++ b/arch/arm/mach-ns9xxx/mach-cc9p9360dev.c
@@ -0,0 +1,41 @@
+/*
+ * arch/arm/mach-ns9xxx/mach-cc9p9360dev.c
+ *
+ * Copyright (C) 2006 by Digi International Inc.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ */
+#include <asm/mach/arch.h>
+#include <asm/mach-types.h>
+
+#include "board-a9m9750dev.h"
+#include "generic.h"
+
+static void __init mach_cc9p9360dev_map_io(void)
+{
+       ns9xxx_map_io();
+       board_a9m9750dev_map_io();
+}
+
+static void __init mach_cc9p9360dev_init_irq(void)
+{
+       ns9xxx_init_irq();
+       board_a9m9750dev_init_irq();
+}
+
+static void __init mach_cc9p9360dev_init_machine(void)
+{
+       ns9xxx_init_machine();
+       board_a9m9750dev_init_machine();
+}
+
+MACHINE_START(CC9P9360DEV, "Connect Core 9P 9360 on an A9M9750 Devboard")
+       .map_io = mach_cc9p9360dev_map_io,
+       .init_irq = mach_cc9p9360dev_init_irq,
+       .init_machine = mach_cc9p9360dev_init_machine,
+       .timer = &ns9xxx_timer,
+       .boot_params = 0x100,
+MACHINE_END
diff --git a/arch/arm/mach-ns9xxx/time.c b/arch/arm/mach-ns9xxx/time.c
new file mode 100644
index 0000000..eec05f1
--- /dev/null
+++ b/arch/arm/mach-ns9xxx/time.c
@@ -0,0 +1,88 @@
+/*
+ * arch/arm/mach-ns9xxx/time.c
+ *
+ * Copyright (C) 2006 by Digi International Inc.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ */
+#include <linux/jiffies.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <asm/arch-ns9xxx/regs-sys.h>
+#include <asm/arch-ns9xxx/clock.h>
+#include <asm/arch-ns9xxx/irqs.h>
+#include <asm/arch/system.h>
+#include "generic.h"
+
+#define TIMERCLOCKSELECT 64
+
+static u32 usecs_per_tick;
+
+static irqreturn_t
+ns9xxx_timer_interrupt(int irq, void *dev_id)
+{
+       write_seqlock(&xtime_lock);
+       timer_tick();
+       write_sequnlock(&xtime_lock);
+
+       return IRQ_HANDLED;
+}
+
+static unsigned long ns9xxx_timer_gettimeoffset(void)
+{
+       /* return the microseconds which have passed since the last interrupt
+        * was _serviced_.  That is, if an interrupt is pending or the counter
+        * reloads, return one periode more. */
+
+       u32 counter1 = SYS_TR(0);
+       int pending = SYS_ISR & (1 << IRQ_TIMER0);
+       u32 counter2 = SYS_TR(0);
+       u32 elapsed;
+
+       if (pending || counter2 > counter1)
+               elapsed = 2 * SYS_TRC(0) - counter2;
+       else
+               elapsed = SYS_TRC(0) - counter1;
+
+       return (elapsed * usecs_per_tick) >> 16;
+
+}
+
+static struct irqaction ns9xxx_timer_irq = {
+       .name = "NS9xxx Timer Tick",
+       .flags = IRQF_DISABLED | IRQF_TIMER,
+       .handler = ns9xxx_timer_interrupt,
+};
+
+static void __init ns9xxx_timer_init(void)
+{
+       int tc;
+
+       usecs_per_tick =
+               SH_DIV(1000000 * TIMERCLOCKSELECT, ns9xxx_cpuclock(), 16);
+
+       /* disable timer */
+       if ((tc = SYS_TC(0)) & SYS_TCx_TEN)
+               SYS_TC(0) = tc & ~SYS_TCx_TEN;
+
+       SYS_TRC(0) = SH_DIV(ns9xxx_cpuclock(), (TIMERCLOCKSELECT * HZ), 0);
+
+       REGSET(tc, SYS_TCx, TEN, EN);
+       REGSET(tc, SYS_TCx, TLCS, DIV64); /* This must match TIMERCLOCKSELECT */
+       REGSET(tc, SYS_TCx, INTS, EN);
+       REGSET(tc, SYS_TCx, UDS, DOWN);
+       REGSET(tc, SYS_TCx, TDBG, STOP);
+       REGSET(tc, SYS_TCx, TSZ, 32);
+       REGSET(tc, SYS_TCx, REN, EN);
+       SYS_TC(0) = tc;
+
+       setup_irq(IRQ_TIMER0, &ns9xxx_timer_irq);
+}
+
+struct sys_timer ns9xxx_timer = {
+       .init = ns9xxx_timer_init,
+       .offset = ns9xxx_timer_gettimeoffset,
+};
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index aade2f7..2762444 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -171,8 +171,8 @@ config CPU_ARM925T
 # ARM926T
 config CPU_ARM926T
        bool "Support ARM926T processor"
-       depends on ARCH_INTEGRATOR || ARCH_VERSATILE_PB || MACH_VERSATILE_AB || 
ARCH_OMAP730 || ARCH_OMAP16XX || MACH_REALVIEW_EB || ARCH_PNX4008 || ARCH_NETX 
|| CPU_S3C2412 || ARCH_AT91SAM9260 || ARCH_AT91SAM9261
-       default y if ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || 
ARCH_OMAP16XX || ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || ARCH_AT91SAM9260 
|| ARCH_AT91SAM9261
+       depends on ARCH_INTEGRATOR || ARCH_VERSATILE_PB || MACH_VERSATILE_AB || 
ARCH_OMAP730 || ARCH_OMAP16XX || MACH_REALVIEW_EB || ARCH_PNX4008 || ARCH_NETX 
|| CPU_S3C2412 || ARCH_AT91SAM9260 || ARCH_AT91SAM9261 || ARCH_NS9XXX
+       default y if ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || 
ARCH_OMAP16XX || ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || ARCH_AT91SAM9260 
|| ARCH_AT91SAM9261 || ARCH_NS9XXX
        select CPU_32v5
        select CPU_ABRT_EV5TJ
        select CPU_CACHE_VIVT
diff --git a/include/asm-arm/arch-ns9xxx/board.h 
b/include/asm-arm/arch-ns9xxx/board.h
new file mode 100644
index 0000000..91dc8fb
--- /dev/null
+++ b/include/asm-arm/arch-ns9xxx/board.h
@@ -0,0 +1,18 @@
+/*
+ * include/asm-arm/arch-ns9xxx/board.h
+ *
+ * Copyright (C) 2006 by Digi International Inc.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ */
+#ifndef __ASM_ARCH_BOARD_H
+#define __ASM_ARCH_BOARD_H
+
+#include <asm/mach-types.h>
+
+#define board_is_a9m9750dev()  (machine_is_cc9p9360dev())
+
+#endif /* ifndef __ASM_ARCH_BOARD_H */
diff --git a/include/asm-arm/arch-ns9xxx/clock.h 
b/include/asm-arm/arch-ns9xxx/clock.h
new file mode 100644
index 0000000..4371a48
--- /dev/null
+++ b/include/asm-arm/arch-ns9xxx/clock.h
@@ -0,0 +1,37 @@
+/*
+ * include/asm-arm/arch-ns9xxx/clock.h
+ *
+ * Copyright (C) 2007 by Digi International Inc.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ */
+#ifndef __ASM_ARCH_CLOCK_H
+#define __ASM_ARCH_CLOCK_H
+
+static inline u32 ns9xxx_systemclock(void)
+{
+       /*
+        * This should be a multiple of HZ * TIMERCLOCKSELECT (in time.c)
+        */
+       return 353894400;
+}
+
+static inline const u32 ns9xxx_cpuclock(void)
+{
+       return ns9xxx_systemclock() / 2;
+}
+
+static inline const u32 ns9xxx_ahbclock(void)
+{
+       return ns9xxx_systemclock() / 4;
+}
+
+static inline const u32 ns9xxx_bbusclock(void)
+{
+       return ns9xxx_systemclock() / 8;
+}
+
+#endif /* ifndef __ASM_ARCH_CLOCK_H */
diff --git a/include/asm-arm/arch-ns9xxx/debug-macro.S 
b/include/asm-arm/arch-ns9xxx/debug-macro.S
new file mode 100644
index 0000000..b21b93e
--- /dev/null
+++ b/include/asm-arm/arch-ns9xxx/debug-macro.S
@@ -0,0 +1,22 @@
+/*
+ * include/asm-arm/arch-ns9xxx/debug-macro.S
+ * Copyright (C) 2006 by Digi International Inc.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ */
+#include <asm/hardware.h>
+
+#include <asm/arch-ns9xxx/regs-board-a9m9750dev.h>
+
+               .macro  addruart,rx
+               mrc     p15, 0, \rx, c1, c0
+               tst     \rx, #1
+               ldreq   \rx, =NS9XXX_CSxSTAT_PHYS(0)
+               ldrne   \rx, =io_p2v(NS9XXX_CSxSTAT_PHYS(0))
+               .endm
+
+#define UART_SHIFT     2
+#include <asm/hardware/debug-8250.S>
diff --git a/include/asm-arm/arch-ns9xxx/dma.h 
b/include/asm-arm/arch-ns9xxx/dma.h
new file mode 100644
index 0000000..a67cbbe
--- /dev/null
+++ b/include/asm-arm/arch-ns9xxx/dma.h
@@ -0,0 +1,14 @@
+/*
+ * include/asm-arm/arch-ns9xxx/dma.h
+ *
+ * Copyright (C) 2006 by Digi International Inc.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ */
+#ifndef __ASM_ARCH_DMA_H
+#define __ASM_ARCH_DMA_H
+
+#endif /* ifndef __ASM_ARCH_DMA_H */
diff --git a/include/asm-arm/arch-ns9xxx/entry-macro.S 
b/include/asm-arm/arch-ns9xxx/entry-macro.S
new file mode 100644
index 0000000..467a198
--- /dev/null
+++ b/include/asm-arm/arch-ns9xxx/entry-macro.S
@@ -0,0 +1,22 @@
+/*
+ * include/asm-arm/arch-ns9xxx/entry-macro.S
+ *
+ * Copyright (C) 2006 by Digi International Inc.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ */
+#include <asm/hardware.h>
+#include <asm/arch-ns9xxx/regs-sys.h>
+
+               .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
+               ldr     \base, =SYS_ISRADDR
+               ldr     \irqstat, [\base, #(SYS_ISA - SYS_ISRADDR)]
+               cmp     \irqstat, #0
+               ldrne   \irqnr, [\base]
+               .endm
+
+               .macro  disable_fiq
+               .endm
diff --git a/include/asm-arm/arch-ns9xxx/hardware.h 
b/include/asm-arm/arch-ns9xxx/hardware.h
new file mode 100644
index 0000000..6819da7
--- /dev/null
+++ b/include/asm-arm/arch-ns9xxx/hardware.h
@@ -0,0 +1,67 @@
+/*
+ * include/asm-arm/arch-ns9xxx/hardware.h
+ *
+ * Copyright (C) 2006 by Digi International Inc.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ */
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H
+
+#include <asm/memory.h>
+
+/*
+ * NetSilicon NS9xxx internal mapping:
+ *
+ * physical                <--> virtual
+ * 0x90000000 - 0x906fffff <--> 0xf9000000 - 0xf96fffff
+ * 0xa0100000 - 0xa0afffff <--> 0xfa100000 - 0xfaafffff
+ */
+#define io_p2v(x)      (0xf0000000 \
+                        + (((x) & 0xf0000000) >> 4) \
+                        + ((x) & 0x00ffffff))
+
+#define io_v2p(x)      ((((x) & 0x0f000000) << 4) \
+                        + ((x) & 0x00ffffff))
+
+#define __REGBIT(bit)          ((u32)1 << (bit))
+#define __REGBITS(hbit, lbit)  ((((u32)1 << ((hbit) - (lbit) + 1)) - 1) << 
(lbit))
+#define __REGVAL(mask, value)  (((value) * ((mask) & (-(mask))) & (mask)))
+
+#ifndef __ASSEMBLY__
+
+#  define __REG(x)     (*((volatile u32 *)io_p2v((x))))
+#  define __REG2(x, y) (*((volatile u32 *)io_p2v((x)) + (y)))
+
+#  define __REGB(x)    (*((volatile u8 *)io_p2v((x))))
+#  define __REGB2(x)   (*((volatile u8 *)io_p2v((x)) + (y)))
+
+#  define REGSET(var, reg, field, value)                               \
+       ((var) = (((var)                                                \
+                  & ~(reg ## _ ## field &                              \
+                      ~ reg ## _ ## field ## _ ## value))              \
+                 | (reg ## _ ## field ## _ ## value)))
+
+#  define REGSETIM(var, reg, field, value)                             \
+       ((var) = (((var)                                                \
+                  & ~(reg ## _ ## field &                              \
+                      ~(__REGVAL(reg ## _ ## field, value))))          \
+                 | (__REGVAL(reg ## _ ## field, value))))
+
+#  define REGGET(reg, field)                                           \
+       ((reg & (reg ## _ ## field)) / (field & (-field)))
+
+#else
+
+#  define __REG(x)     io_p2v(x)
+#  define __REG2(x, y) io_p2v((x) + (y))
+
+#  define __REGB(x)    __REG((x))
+#  define __REGB2(x, y)        __REG2((x), (y))
+
+#endif
+
+#endif /* ifndef __ASM_ARCH_HARDWARE_H */
diff --git a/include/asm-arm/arch-ns9xxx/io.h b/include/asm-arm/arch-ns9xxx/io.h
new file mode 100644
index 0000000..6f82d28
--- /dev/null
+++ b/include/asm-arm/arch-ns9xxx/io.h
@@ -0,0 +1,20 @@
+/*
+ * include/asm-arm/arch-ns9xxx/io.h
+ *
+ * Copyright (C) 2006 by Digi International Inc.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ */
+#ifndef __ASM_ARCH_IO_H
+#define __ASM_ARCH_IO_H
+
+#define IO_SPACE_LIMIT  0xffffffff /* XXX */
+
+#define __io(a)         ((void __iomem *)(a))
+#define __mem_pci(a)    (a)
+#define __mem_isa(a)    (IO_BASE + (a))
+
+#endif /* ifndef __ASM_ARCH_IO_H */
diff --git a/include/asm-arm/arch-ns9xxx/irqs.h 
b/include/asm-arm/arch-ns9xxx/irqs.h
new file mode 100644
index 0000000..25d8d28
--- /dev/null
+++ b/include/asm-arm/arch-ns9xxx/irqs.h
@@ -0,0 +1,85 @@
+/*
+ * include/asm-arm/arch-ns9xxx/irqs.h
+ *
+ * Copyright (C) 2006 by Digi International Inc.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ */
+#ifndef __ASM_ARCH_IRQS_H
+#define __ASM_ARCH_IRQS_H
+
+#define IRQ_WATCHDOG   0
+#define IRQ_AHBBUSERR  1
+#define IRQ_BBUSAGG    2
+/* irq 3 is reserved for NS9360 */
+#define IRQ_ETHRX      4
+#define IRQ_ETHTX      5
+#define IRQ_ETHPHY     6
+#define IRQ_LCD                7
+#define IRQ_SERBRX     8
+#define IRQ_SERBTX     9
+#define IRQ_SERARX     10
+#define IRQ_SERATX     11
+#define IRQ_SERCRX     12
+#define IRQ_SERCTX     13
+#define IRQ_I2C                14
+#define IRQ_BBUSDMA    15
+#define IRQ_TIMER0     16
+#define IRQ_TIMER1     17
+#define IRQ_TIMER2     18
+#define IRQ_TIMER3     19
+#define IRQ_TIMER4     20
+#define IRQ_TIMER5     21
+#define IRQ_TIMER6     22
+#define IRQ_TIMER7     23
+#define IRQ_RTC                24
+#define IRQ_USBHOST    25
+#define IRQ_USBDEVICE  26
+#define IRQ_IEEE1284   27
+#define IRQ_EXT0       28
+#define IRQ_EXT1       29
+#define IRQ_EXT2       30
+#define IRQ_EXT3       31
+
+#define BBUS_IRQ(irq)  (32 + irq)
+
+#define IRQ_BBUS_DMA           BBUS_IRQ(0)
+#define IRQ_BBUS_SERBRX                BBUS_IRQ(2)
+#define IRQ_BBUS_SERBTX                BBUS_IRQ(3)
+#define IRQ_BBUS_SERARX                BBUS_IRQ(4)
+#define IRQ_BBUS_SERATX                BBUS_IRQ(5)
+#define IRQ_BBUS_SERCRX                BBUS_IRQ(6)
+#define IRQ_BBUS_SERCTX                BBUS_IRQ(7)
+#define IRQ_BBUS_SERDRX                BBUS_IRQ(8)
+#define IRQ_BBUS_SERDTX                BBUS_IRQ(9)
+#define IRQ_BBUS_I2C           BBUS_IRQ(10)
+#define IRQ_BBUS_1284          BBUS_IRQ(11)
+#define IRQ_BBUS_UTIL          BBUS_IRQ(12)
+#define IRQ_BBUS_RTC           BBUS_IRQ(13)
+#define IRQ_BBUS_USBHST                BBUS_IRQ(14)
+#define IRQ_BBUS_USBDEV                BBUS_IRQ(15)
+#define IRQ_BBUS_AHBDMA1       BBUS_IRQ(24)
+#define IRQ_BBUS_AHBDMA2       BBUS_IRQ(25)
+
+/*
+ * these Interrupts are specific for the a9m9750dev board.
+ * They are generated by an FPGA that interrupts the CPU on
+ * IRQ_EXT2
+ */
+#define FPGA_IRQ(irq)  (64 + irq)
+
+#define IRQ_FPGA_UARTA         FPGA_IRQ(0)
+#define IRQ_FPGA_UARTB         FPGA_IRQ(1)
+#define IRQ_FPGA_UARTC         FPGA_IRQ(2)
+#define IRQ_FPGA_UARTD         FPGA_IRQ(3)
+#define IRQ_FPGA_TOUCH         FPGA_IRQ(4)
+#define IRQ_FPGA_CF            FPGA_IRQ(5)
+#define IRQ_FPGA_CAN0          FPGA_IRQ(6)
+#define IRQ_FPGA_CAN1          FPGA_IRQ(7)
+
+#define NR_IRQS        72
+
+#endif /* __ASM_ARCH_IRQS_H */
diff --git a/include/asm-arm/arch-ns9xxx/memory.h 
b/include/asm-arm/arch-ns9xxx/memory.h
new file mode 100644
index 0000000..ce1343e
--- /dev/null
+++ b/include/asm-arm/arch-ns9xxx/memory.h
@@ -0,0 +1,27 @@
+/*
+ * include/asm-arm/arch-ns9xxx/memory.h
+ *
+ * Copyright (C) 2006 by Digi International Inc.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+*/
+#ifndef __ASM_ARCH_MEMORY_H
+#define __ASM_ARCH_MEMORY_H
+
+/* x in [0..3] */
+#define NS9XXX_CSxSTAT_PHYS(x) UL(((x) + 4) << 28)
+
+#define NS9XXX_CS0STAT_LENGTH  UL(0x1000)
+#define NS9XXX_CS1STAT_LENGTH  UL(0x1000)
+#define NS9XXX_CS2STAT_LENGTH  UL(0x1000)
+#define NS9XXX_CS3STAT_LENGTH  UL(0x1000)
+
+#define PHYS_OFFSET    UL(0x00000000)
+
+#define __virt_to_bus(x) __virt_to_phys(x)
+#define __bus_to_virt(x) __phys_to_virt(x)
+
+#endif
diff --git a/include/asm-arm/arch-ns9xxx/processor.h 
b/include/asm-arm/arch-ns9xxx/processor.h
new file mode 100644
index 0000000..716c106
--- /dev/null
+++ b/include/asm-arm/arch-ns9xxx/processor.h
@@ -0,0 +1,18 @@
+/*
+ * include/asm-arm/arch-ns9xxx/processor.h
+ *
+ * Copyright (C) 2006 by Digi International Inc.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ */
+#ifndef __ASM_ARCH_PROCESSOR_H
+#define __ASM_ARCH_PROCESSOR_H
+
+#include <asm/mach-types.h>
+
+#define processor_is_ns9360()  (machine_is_cc9p9360dev())
+
+#endif /* ifndef __ASM_ARCH_PROCESSOR_H */
diff --git a/include/asm-arm/arch-ns9xxx/regs-bbu.h 
b/include/asm-arm/arch-ns9xxx/regs-bbu.h
new file mode 100644
index 0000000..e262695
--- /dev/null
+++ b/include/asm-arm/arch-ns9xxx/regs-bbu.h
@@ -0,0 +1,21 @@
+/*
+ * include/asm-arm/arch-ns9xxx/regs-bbu.h
+ *
+ * Copyright (C) 2006 by Digi International Inc.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ */
+#ifndef __ASM_ARCH_REGSBBU_H
+#define __ASM_ARCH_REGSBBU_H
+
+#include <asm/hardware.h>
+
+/* BBus Utility */
+
+/* GPIO Configuration Register */
+#define BBU_GC(x)      __REG2(0x9060000c, (x))
+
+#endif /* ifndef __ASM_ARCH_REGSBBU_H */
diff --git a/include/asm-arm/arch-ns9xxx/regs-board-a9m9750dev.h 
b/include/asm-arm/arch-ns9xxx/regs-board-a9m9750dev.h
new file mode 100644
index 0000000..c3dc532
--- /dev/null
+++ b/include/asm-arm/arch-ns9xxx/regs-board-a9m9750dev.h
@@ -0,0 +1,24 @@
+/*
+ * include/asm-arm/arch-ns9xxx/regs-board-a9m9750dev.h
+ *
+ * Copyright (C) 2006 by Digi International Inc.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ */
+#ifndef __ASM_ARCH_REGSBOARDA9M9750_H
+#define __ASM_ARCH_REGSBOARDA9M9750_H
+
+#include <asm/hardware.h>
+
+#define FPGA_UARTA_BASE        io_p2v(NS9XXX_CSxSTAT_PHYS(0))
+#define FPGA_UARTB_BASE        io_p2v(NS9XXX_CSxSTAT_PHYS(0) + 0x08)
+#define FPGA_UARTC_BASE        io_p2v(NS9XXX_CSxSTAT_PHYS(0) + 0x10)
+#define FPGA_UARTD_BASE        io_p2v(NS9XXX_CSxSTAT_PHYS(0) + 0x18)
+
+#define FPGA_IER       __REGB(NS9XXX_CSxSTAT_PHYS(0) + 0x50)
+#define FPGA_ISR       __REGB(NS9XXX_CSxSTAT_PHYS(0) + 0x60)
+
+#endif /* ifndef __ASM_ARCH_REGSBOARDA9M9750_H */
diff --git a/include/asm-arm/arch-ns9xxx/regs-mem.h 
b/include/asm-arm/arch-ns9xxx/regs-mem.h
new file mode 100644
index 0000000..8ed8448
--- /dev/null
+++ b/include/asm-arm/arch-ns9xxx/regs-mem.h
@@ -0,0 +1,135 @@
+/*
+ * include/asm-arm/arch-ns9xxx/regs-mem.h
+ *
+ * Copyright (C) 2006 by Digi International Inc.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ */
+#ifndef __ASM_ARCH_REGSMEM_H
+#define __ASM_ARCH_REGSMEM_H
+
+#include <asm/hardware.h>
+
+/* Memory Module */
+
+/* Control register */
+#define MEM_CTRL       __REG(0xa0700000)
+
+/* Status register */
+#define MEM_STAT       __REG(0xa0700004)
+
+/* Configuration register */
+#define MEM_CONF       __REG(0xa0700008)
+
+/* Dynamic Memory Control register */
+#define MEM_DMCTRL     __REG(0xa0700020)
+
+/* Dynamic Memory Refresh Timer */
+#define MEM_DMRT       __REG(0xa0700024)
+
+/* Dynamic Memory Read Configuration register */
+#define MEM_DMRC       __REG(0xa0700028)
+
+/* Dynamic Memory Precharge Command Period (tRP) */
+#define MEM_DMPCP      __REG(0xa0700030)
+
+/* Dynamic Memory Active to Precharge Command Period (tRAS) */
+#define MEM_DMAPCP     __REG(0xa0700034)
+
+/* Dynamic Memory Self-Refresh Exit Time (tSREX) */
+#define MEM_DMSRET     __REG(0xa0700038)
+
+/* Dynamic Memory Last Data Out to Active Time (tAPR) */
+#define MEM_DMLDOAT    __REG(0xa070003c)
+
+/* Dynamic Memory Data-in to Active Command Time (tDAL or TAPW) */
+#define MEM_DMDIACT    __REG(0xa0700040)
+
+/* Dynamic Memory Write Recovery Time (tWR, tDPL, tRWL, tRDL) */
+#define MEM_DMWRT      __REG(0xa0700044)
+
+/* Dynamic Memory Active to Active Command Period (tRC) */
+#define MEM_DMAACP     __REG(0xa0700048)
+
+/* Dynamic Memory Auto Refresh Period, and Auto Refresh to Active Command 
Period (tRFC) */
+#define MEM_DMARP      __REG(0xa070004c)
+
+/* Dynamic Memory Exit Self-Refresh to Active Command (tXSR) */
+#define MEM_DMESRAC    __REG(0xa0700050)
+
+/* Dynamic Memory Active Bank A to Active B Time (tRRD) */
+#define MEM_DMABAABT   __REG(0xa0700054)
+
+/* Dynamic Memory Load Mode register to Active Command Time (tMRD) */
+#define MEM_DMLMACT    __REG(0xa0700058)
+
+/* Static Memory Extended Wait */
+#define MEM_SMEW       __REG(0xa0700080)
+
+/* Dynamic Memory Configuration Register x */
+#define MEM_DMCONF(x)  __REG2(0xa0700100, (x) << 3)
+
+/* Dynamic Memory RAS and CAS Delay x */
+#define MEM_DMRCD(x)   __REG2(0xa0700104, (x) << 3)
+
+/* Static Memory Configuration Register x */
+#define MEM_SMC(x)     __REG2(0xa0700200, (x) << 3)
+
+/* Static Memory Configuration Register x: Write protect */
+#define MEM_SMC_WSMC           __REGBIT(20)
+#define MEM_SMC_WSMC_OFF               __REGVAL(MEM_SMC_WSMC, 0)
+#define MEM_SMC_WSMC_ON                        __REGVAL(MEM_SMC_WSMC, 1)
+
+/* Static Memory Configuration Register x: Buffer enable */
+#define MEM_SMC_BSMC           __REGBIT(19)
+#define MEM_SMC_BSMC_OFF               __REGVAL(MEM_SMC_BSMC, 0)
+#define MEM_SMC_BSMC_ON                        __REGVAL(MEM_SMC_BSMC, 1)
+
+/* Static Memory Configuration Register x: Extended Wait */
+#define MEM_SMC_EW             __REGBIT(8)
+#define MEM_SMC_EW_OFF                 __REGVAL(MEM_SMC_EW, 0)
+#define MEM_SMC_EW_ON                  __REGVAL(MEM_SMC_EW, 1)
+
+/* Static Memory Configuration Register x: Byte lane state */
+#define MEM_SMC_PB             __REGBIT(7)
+#define MEM_SMC_PB_0                   __REGVAL(MEM_SMC_PB, 0)
+#define MEM_SMC_PB_1                   __REGVAL(MEM_SMC_PB, 1)
+
+/* Static Memory Configuration Register x: Chip select polarity */
+#define MEM_SMC_PC             __REGBIT(6)
+#define MEM_SMC_PC_AL                  __REGVAL(MEM_SMC_PC, 0)
+#define MEM_SMC_PC_AH                  __REGVAL(MEM_SMC_PC, 1)
+
+/* static memory configuration register x: page mode*/
+#define MEM_SMC_PM             __REGBIT(3)
+#define MEM_SMC_PM_DIS                 __REGVAL(MEM_SMC_PM, 0)
+#define MEM_SMC_PM_ASYNC               __REGVAL(MEM_SMC_PM, 1)
+
+/* static memory configuration register x: Memory width */
+#define MEM_SMC_MW             __REGBITS(1, 0)
+#define MEM_SMC_MW_8                   __REGVAL(MEM_SMC_MW, 0)
+#define MEM_SMC_MW_16                  __REGVAL(MEM_SMC_MW, 1)
+#define MEM_SMC_MW_32                  __REGVAL(MEM_SMC_MW, 2)
+
+/* Static Memory Write Enable Delay x */
+#define MEM_SMWED(x)   __REG2(0xa0700204, (x) << 3)
+
+/* Static Memory Output Enable Delay x */
+#define MEM_SMOED(x)   __REG2(0xa0700208, (x) << 3)
+
+/* Static Memory Read Delay x */
+#define MEM_SMRD(x)    __REG2(0xa070020c, (x) << 3)
+
+/* Static Memory Page Mode Read Delay 0 */
+#define MEM_SMPMRD(x)  __REG2(0xa0700210, (x) << 3)
+
+/* Static Memory Write Delay */
+#define MEM_SMWD(x)    __REG2(0xa0700214, (x) << 3)
+
+/* Static Memory Turn Round Delay x */
+#define MEM_SWT(x)     __REG2(0xa0700218, (x) << 3)
+
+#endif /* ifndef __ASM_ARCH_REGSMEM_H */
diff --git a/include/asm-arm/arch-ns9xxx/regs-sys.h 
b/include/asm-arm/arch-ns9xxx/regs-sys.h
new file mode 100644
index 0000000..8162a50
--- /dev/null
+++ b/include/asm-arm/arch-ns9xxx/regs-sys.h
@@ -0,0 +1,157 @@
+/*
+ * include/asm-arm/arch-ns9xxx/regs-sys.h
+ *
+ * Copyright (C) 2006 by Digi International Inc.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ */
+#ifndef __ASM_ARCH_REGSSYS_H
+#define __ASM_ARCH_REGSSYS_H
+
+#include <asm/hardware.h>
+
+/* System Control Module */
+
+/* AHB Arbiter Gen Configuration */
+#define SYS_AHBAGENCONF        __REG(0xa0900000)
+
+/* BRC */
+#define SYS_BRC(x)     __REG2(0xa0900004, (x))
+
+/* Timer x Reload Count register */
+#define SYS_TRC(x)     __REG2(0xa0900044, (x))
+
+/* Timer x Read register */
+#define SYS_TR(x)      __REG2(0xa0900084, (x))
+
+/* Interrupt Vector Address Register Level x */
+#define SYS_IVA(x)     __REG2(0xa09000c4, (x))
+
+/* Interrupt Configuration registers */
+#define SYS_IC(x)      __REG2(0xa0900144, (x))
+
+/* ISRADDR */
+#define SYS_ISRADDR    __REG(0xa0900164)
+
+/* Interrupt Status Active */
+#define SYS_ISA                __REG(0xa0900168)
+
+/* Interrupt Status Raw */
+#define SYS_ISR                __REG(0xa090016c)
+
+/* Timer Interrupt Status register */
+#define SYS_TIS                __REG(0xa0900170)
+
+/* PLL Configuration register */
+#define SYS_PLL                __REG(0xa0900188)
+
+/* PLL Configuration register: PLL SW change */
+#define SYS_PLL_SWC            __REGBIT(15)
+#define SYS_PLL_SWC_NO                 __REGVAL(SYS_PLL_SWC, 0)
+#define SYS_PLL_SWC_YES                        __REGVAL(SYS_PLL_SWC, 1)
+
+/* Timer x Control register */
+#define SYS_TC(x)      __REG2(0xa0900190, (x))
+
+/* Timer x Control register: Timer enable */
+#define SYS_TCx_TEN            __REGBIT(15)
+#define SYS_TCx_TEN_DIS                        __REGVAL(SYS_TCx_TEN, 1)
+#define SYS_TCx_TEN_EN                 __REGVAL(SYS_TCx_TEN, 1)
+
+/* Timer x Control register: CPU debug mode */
+#define SYS_TCx_TDBG           __REGBIT(10)
+#define SYS_TCx_TDBG_CONT              __REGVAL(SYS_TCx_TDBG, 0)
+#define SYS_TCx_TDBG_STOP              __REGVAL(SYS_TCx_TDBG, 1)
+
+/* Timer x Control register: Interrupt clear */
+#define SYS_TCx_INTC           __REGBIT(9)
+#define SYS_TCx_INTC_UNSET             __REGVAL(SYS_TCx_INTC, 0)
+#define SYS_TCx_INTC_SET               __REGVAL(SYS_TCx_INTC, 1)
+
+/* Timer x Control register: Timer clock select */
+#define SYS_TCx_TLCS           __REGBITS(8, 6)
+#define SYS_TCx_TLCS_CPU               __REGVAL(SYS_TCx_TLCS, 0)       /* CPU 
clock */
+#define SYS_TCx_TLCS_DIV2              __REGVAL(SYS_TCx_TLCS, 1)       /* CPU 
clock / 2 */
+#define SYS_TCx_TLCS_DIV4              __REGVAL(SYS_TCx_TLCS, 2)       /* CPU 
clock / 4 */
+#define SYS_TCx_TLCS_DIV8              __REGVAL(SYS_TCx_TLCS, 3)       /* CPU 
clock / 8 */
+#define SYS_TCx_TLCS_DIV16             __REGVAL(SYS_TCx_TLCS, 4)       /* CPU 
clock / 16 */
+#define SYS_TCx_TLCS_DIV32             __REGVAL(SYS_TCx_TLCS, 5)       /* CPU 
clock / 32 */
+#define SYS_TCx_TLCS_DIV64             __REGVAL(SYS_TCx_TLCS, 6)       /* CPU 
clock / 64 */
+#define SYS_TCx_TLCS_EXT               __REGVAL(SYS_TCx_TLCS, 7)
+
+/* Timer x Control register: Timer mode */
+#define SYS_TCx_TM             __REGBITS(5, 4)
+#define SYS_TCx_TM_IEE                 __REGVAL(SYS_TCx_TM, 0)         /* 
Internal timer or external event */
+#define SYS_TCx_TM_ELL                 __REGVAL(SYS_TCx_TM, 1)         /* 
External low-level, gated timer */
+#define SYS_TCx_TM_EHL                 __REGVAL(SYS_TCx_TM, 2)         /* 
External high-level, gated timer */
+#define SYS_TCx_TM_CONCAT              __REGVAL(SYS_TCx_TM, 3)         /* 
Concatenate the lower timer. */
+
+/* Timer x Control register: Interrupt select */
+#define SYS_TCx_INTS           __REGBIT(3)
+#define SYS_TCx_INTS_DIS               __REGVAL(SYS_TCx_INTS, 0)
+#define SYS_TCx_INTS_EN                        __REGVAL(SYS_TCx_INTS, 1)
+
+/* Timer x Control register: Up/down select */
+#define SYS_TCx_UDS            __REGBIT(2)
+#define SYS_TCx_UDS_UP                 __REGVAL(SYS_TCx_UDS, 0)
+#define SYS_TCx_UDS_DOWN               __REGVAL(SYS_TCx_UDS, 1)
+
+/* Timer x Control register: 32- or 16-bit timer */
+#define SYS_TCx_TSZ            __REGBIT(1)
+#define SYS_TCx_TSZ_16                 __REGVAL(SYS_TCx_TSZ, 0)
+#define SYS_TCx_TSZ_32                 __REGVAL(SYS_TCx_TSZ, 1)
+
+/* Timer x Control register: Reload enable */
+#define SYS_TCx_REN            __REGBIT(0)
+#define SYS_TCx_REN_DIS                        __REGVAL(SYS_TCx_REN, 0)
+#define SYS_TCx_REN_EN                 __REGVAL(SYS_TCx_REN, 1)
+
+/* System Memory Chip Select x Dynamic Memory Base */
+#define SYS_SMCSDMB(x) __REG2(0xa09001d0, (x) << 1)
+
+/* System Memory Chip Select x Dynamic Memory Mask */
+#define SYS_SMCSDMM(x) __REG2(0xa09001d4, (x) << 1)
+
+/* System Memory Chip Select x Static Memory Base */
+#define SYS_SMCSSMB(x) __REG2(0xa09001f0, (x) << 1)
+
+/* System Memory Chip Select x Static Memory Base: Chip select x base */
+#define SYS_SMCSSMB_CSxB       __REGBITS(31, 12)
+
+/* System Memory Chip Select x Static Memory Mask */
+#define SYS_SMCSSMM(x) __REG2(0xa09001f4, (x) << 1)
+
+/* System Memory Chip Select x Static Memory Mask: Chip select x mask */
+#define SYS_SMCSSMM_CSxM       __REGBITS(31, 12)
+
+/* System Memory Chip Select x Static Memory Mask: Chip select x enable */
+#define SYS_SMCSSMM_CSEx       __REGBIT(0)
+#define SYS_SMCSSMM_CSEx_DIS           __REGVAL(SYS_SMCSSMM_CSEx, 0)
+#define SYS_SMCSSMM_CSEx_EN            __REGVAL(SYS_SMCSSMM_CSEx, 1)
+
+/* General purpose, user-defined ID register */
+#define SYS_GENID      __REG(0xa0900210)
+
+/* External Interrupt x Control register */
+#define SYS_EIC(x)     __REG2(0xa0900214, (x))
+
+/* External Interrupt x Control register: Status */
+#define SYS_EIC_STS            __REGBIT(3)
+
+/* External Interrupt x Control register: Clear */
+#define SYS_EIC_CLR            __REGBIT(2)
+
+/* External Interrupt x Control register: Polarity */
+#define SYS_EIC_PLTY           __REGBIT(1)
+#define SYS_EIC_PLTY_AH                        __REGVAL(SYS_EIC_PLTY, 0)
+#define SYS_EIC_PLTY_AL                        __REGVAL(SYS_EIC_PLTY, 1)
+
+/* External Interrupt x Control register: Level edge */
+#define SYS_EIC_LVEDG          __REGBIT(0)
+#define SYS_EIC_LVEDG_LEVEL            __REGVAL(SYS_EIC_LVEDG, 0)
+#define SYS_EIC_LVEDG_EDGE             __REGVAL(SYS_EIC_LVEDG, 1)
+
+#endif /* ifndef __ASM_ARCH_REGSSYS_H */
diff --git a/include/asm-arm/arch-ns9xxx/system.h 
b/include/asm-arm/arch-ns9xxx/system.h
new file mode 100644
index 0000000..e3cd4d3
--- /dev/null
+++ b/include/asm-arm/arch-ns9xxx/system.h
@@ -0,0 +1,34 @@
+/*
+ * include/asm-arm/arch-ns9xxx/system.h
+ *
+ * Copyright (C) 2006 by Digi International Inc.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ */
+#ifndef __ASM_ARCH_SYSTEM_H
+#define __ASM_ARCH_SYSTEM_H
+
+#include <asm/proc-fns.h>
+#include <asm/arch-ns9xxx/regs-sys.h>
+#include <asm/mach-types.h>
+
+static inline void arch_idle(void)
+{
+       cpu_do_idle();
+}
+
+static inline void arch_reset(char mode)
+{
+       u32 reg;
+
+       reg = SYS_PLL >> 16;
+       REGSET(reg, SYS_PLL, SWC, YES);
+       SYS_PLL = reg;
+
+       BUG();
+}
+
+#endif /* ifndef __ASM_ARCH_SYSTEM_H */
diff --git a/include/asm-arm/arch-ns9xxx/timex.h 
b/include/asm-arm/arch-ns9xxx/timex.h
new file mode 100644
index 0000000..f776cbd
--- /dev/null
+++ b/include/asm-arm/arch-ns9xxx/timex.h
@@ -0,0 +1,20 @@
+/*
+ * include/asm-arm/arch-ns9xxx/timex.h
+ *
+ * Copyright (C) 2005-2006 by Digi International Inc.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ */
+#ifndef __ASM_ARCH_TIMEX_H
+#define __ASM_ARCH_TIMEX_H
+
+/*
+ * value for CLOCK_TICK_RATE stolen from include/asm-arm/arch-s3c2410/timex.h.
+ * See there for an explanation.
+ */
+#define CLOCK_TICK_RATE         12000000
+
+#endif /* ifndef __ASM_ARCH_TIMEX_H */
diff --git a/include/asm-arm/arch-ns9xxx/uncompress.h 
b/include/asm-arm/arch-ns9xxx/uncompress.h
new file mode 100644
index 0000000..961ca7d
--- /dev/null
+++ b/include/asm-arm/arch-ns9xxx/uncompress.h
@@ -0,0 +1,35 @@
+/*
+ * include/asm-arm/arch-ns9xxx/uncompress.h
+ *
+ * Copyright (C) 2006 by Digi International Inc.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ */
+#ifndef __ASM_ARCH_UNCOMPRESS_H
+#define __ASM_ARCH_UNCOMPRESS_H
+
+static void putc(char c)
+{
+       volatile u8 *base = (volatile u8 *)0x40000000;
+       int t = 0x10000;
+
+       do {
+               if (base[5] & 0x20) {
+                       base[0] = c;
+                       break;
+               }
+       } while (--t);
+}
+
+#define arch_decomp_setup()
+#define arch_decomp_wdog()
+
+static void flush(void)
+{
+       /* nothing */
+}
+
+#endif /* ifndef __ASM_ARCH_UNCOMPRESS_H */
diff --git a/include/asm-arm/arch-ns9xxx/vmalloc.h 
b/include/asm-arm/arch-ns9xxx/vmalloc.h
new file mode 100644
index 0000000..2f3cb6f
--- /dev/null
+++ b/include/asm-arm/arch-ns9xxx/vmalloc.h
@@ -0,0 +1,16 @@
+/*
+ * include/asm-arm/arch-ns9xxx/vmalloc.h
+ *
+ * Copyright (C) 2006 by Digi International Inc.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ */
+#ifndef __ASM_ARCH_VMALLOC_H
+#define __ASM_ARCH_VMALLOC_H
+
+#define VMALLOC_END     (0xf0000000)
+
+#endif /* ifndef __ASM_ARCH_VMALLOC_H */
-
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