Commit:     58e0543e8f355b32f0778a18858b255adb7402ae
Parent:     b1cbf4e4dddd708ba268c3a2bf38383a269d490a
Author:     Eric W. Biederman <[EMAIL PROTECTED]>
AuthorDate: Mon Mar 5 00:30:11 2007 -0800
Committer:  Linus Torvalds <[EMAIL PROTECTED]>
CommitDate: Mon Mar 5 07:57:50 2007 -0800

    [PATCH] msi: support masking msi irqs without a mask bit
    For devices that do not support msi-x we only support 1 interrupt.  
    we can disable that one interrupt by disabling the msi capability itself.  
    we leave the intx interrupts disabled while we have the msi capability
    disabled no interrupts should be delivered from that device.
    Devices with just the minimal msi support (and thus hitting this code path)
    include things like the intel e1000 nic, so it looks like is going to be a
    fairly common case and thus important to get right.
    Signed-off-by: Eric W. Biederman <[EMAIL PROTECTED]>
    Cc: Michael Ellerman <[EMAIL PROTECTED]>
    Cc: Paul Mackerras <[EMAIL PROTECTED]>
    Cc: Benjamin Herrenschmidt <[EMAIL PROTECTED]>
    Signed-off-by: Andrew Morton <[EMAIL PROTECTED]>
    Signed-off-by: Linus Torvalds <[EMAIL PROTECTED]>
 drivers/pci/msi.c |    2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/drivers/pci/msi.c b/drivers/pci/msi.c
index c43e7d2..01869b1 100644
--- a/drivers/pci/msi.c
+++ b/drivers/pci/msi.c
@@ -85,6 +85,8 @@ static void msi_set_mask_bit(unsigned int irq, int flag)
                        mask_bits &= ~(1);
                        mask_bits |= flag;
                        pci_write_config_dword(entry->dev, pos, mask_bits);
+               } else {
+                       msi_set_enable(entry->dev, !flag);
        case PCI_CAP_ID_MSIX:
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