Commit:     7605b3906192a171e651076325b1ed1d5ea57ec9
Parent:     83598f1cb06101e972b1f5aaf3408eb729622fa8
Author:     Ralf Baechle <[EMAIL PROTECTED]>
AuthorDate: Tue Mar 20 13:56:50 2007 +0000
Committer:  Ralf Baechle <[EMAIL PROTECTED]>
CommitDate: Sat Mar 24 17:01:49 2007 +0000

    [MIPS] Fix pipeline hazard.
    In the the sequence:
            mfc0    $x, $status
    the mfc0 may not see the SR_IE bit set. This was a deliberate bug in the
    kernel code because we knew this was a safe thing to do on all R2 silicon
    so far but new silicon is changing this.
    Signed-off-by: Ralf Baechle <[EMAIL PROTECTED]>
 include/asm-mips/hazards.h |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/include/asm-mips/hazards.h b/include/asm-mips/hazards.h
index 5007315..e50c77e 100644
--- a/include/asm-mips/hazards.h
+++ b/include/asm-mips/hazards.h
@@ -52,6 +52,7 @@ ASMMACRO(tlb_probe_hazard,
+        _ehb
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