Gitweb:     
http://git.kernel.org/git/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commit;h=1489f90a49f0603a393e1800d729050f6e332bec
Commit:     1489f90a49f0603a393e1800d729050f6e332bec
Parent:     d420cb44693b8370cbf06c3e31b4b5dec66c9f86
Author:     Andreas Oberritter <[EMAIL PROTECTED]>
AuthorDate: Mon Apr 2 10:44:35 2007 -0300
Committer:  Mauro Carvalho Chehab <[EMAIL PROTECTED]>
CommitDate: Mon Apr 2 11:03:05 2007 -0300

    V4L/DVB (5496): Pluto2: fix incorrect TSCR register setting
    
    The ADEF bits in the TSCR register have different meanings in read and
    write mode. For this reason ADEF has to be reset on every
    read-modify-write operation.
    This patch introduces a special write function for this register, which
    takes care of it.
    
    Thanks to Holger Magnussen for pointing my nose at this problem.
    
    Signed-off-by: Andreas Oberritter <[EMAIL PROTECTED]>
    Signed-off-by: Mauro Carvalho Chehab <[EMAIL PROTECTED]>
---
 drivers/media/dvb/pluto2/pluto2.c |   22 ++++++++++++++--------
 1 files changed, 14 insertions(+), 8 deletions(-)

diff --git a/drivers/media/dvb/pluto2/pluto2.c 
b/drivers/media/dvb/pluto2/pluto2.c
index ffda71d..058df5c 100644
--- a/drivers/media/dvb/pluto2/pluto2.c
+++ b/drivers/media/dvb/pluto2/pluto2.c
@@ -149,6 +149,15 @@ static inline void pluto_rw(struct pluto *pluto, u32 reg, 
u32 mask, u32 bits)
        writel(val, &pluto->io_mem[reg]);
 }
 
+static void pluto_write_tscr(struct pluto *pluto, u32 val)
+{
+       /* set the number of packets */
+       val &= ~TSCR_ADEF;
+       val |= TS_DMA_PACKETS / 2;
+
+       pluto_writereg(pluto, REG_TSCR, val);
+}
+
 static void pluto_setsda(void *data, int state)
 {
        struct pluto *pluto = data;
@@ -213,11 +222,11 @@ static void pluto_reset_ts(struct pluto *pluto, int 
reenable)
 
        if (val & TSCR_RSTN) {
                val &= ~TSCR_RSTN;
-               pluto_writereg(pluto, REG_TSCR, val);
+               pluto_write_tscr(pluto, val);
        }
        if (reenable) {
                val |= TSCR_RSTN;
-               pluto_writereg(pluto, REG_TSCR, val);
+               pluto_write_tscr(pluto, val);
        }
 }
 
@@ -339,7 +348,7 @@ static irqreturn_t pluto_irq(int irq, void *dev_id)
        }
 
        /* ACK the interrupt */
-       pluto_writereg(pluto, REG_TSCR, tscr | TSCR_IACK);
+       pluto_write_tscr(pluto, tscr | TSCR_IACK);
 
        return IRQ_HANDLED;
 }
@@ -348,9 +357,6 @@ static void __devinit pluto_enable_irqs(struct pluto *pluto)
 {
        u32 val = pluto_readreg(pluto, REG_TSCR);
 
-       /* set the number of packets */
-       val &= ~TSCR_ADEF;
-       val |= TS_DMA_PACKETS / 2;
        /* disable AFUL and LOCK interrupts */
        val |= (TSCR_MSKA | TSCR_MSKL);
        /* enable DMA and OVERFLOW interrupts */
@@ -358,7 +364,7 @@ static void __devinit pluto_enable_irqs(struct pluto *pluto)
        /* clear pending interrupts */
        val |= TSCR_IACK;
 
-       pluto_writereg(pluto, REG_TSCR, val);
+       pluto_write_tscr(pluto, val);
 }
 
 static void pluto_disable_irqs(struct pluto *pluto)
@@ -370,7 +376,7 @@ static void pluto_disable_irqs(struct pluto *pluto)
        /* clear pending interrupts */
        val |= TSCR_IACK;
 
-       pluto_writereg(pluto, REG_TSCR, val);
+       pluto_write_tscr(pluto, val);
 }
 
 static int __devinit pluto_hw_init(struct pluto *pluto)
-
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