Gitweb:     
http://git.kernel.org/git/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commit;h=0264f1603904dbee3196abc748a53fb0b23b8046
Commit:     0264f1603904dbee3196abc748a53fb0b23b8046
Parent:     652b9672cfc4000382f0f3f41907d9d32e5bd327
Author:     Paul Mundt <[EMAIL PROTECTED]>
AuthorDate: Wed Mar 28 23:36:03 2007 +0900
Committer:  Paul Mundt <[EMAIL PROTECTED]>
CommitDate: Mon May 7 02:11:55 2007 +0000

    sh: Tidy up L-BOX area5 addresses.
    
    L-BOX can use the normal PA_AREA5_IO, there's no reason for it to
    reproduce it.
    
    Signed-off-by: Paul Mundt <[EMAIL PROTECTED]>
---
 arch/sh/boards/lboxre2/setup.c |    3 ++-
 include/asm-sh/lboxre2.h       |    9 ++-------
 2 files changed, 4 insertions(+), 8 deletions(-)

diff --git a/arch/sh/boards/lboxre2/setup.c b/arch/sh/boards/lboxre2/setup.c
index fc3cba3..4e20f7c 100644
--- a/arch/sh/boards/lboxre2/setup.c
+++ b/arch/sh/boards/lboxre2/setup.c
@@ -15,6 +15,7 @@
 #include <linux/platform_device.h>
 #include <linux/pata_platform.h>
 #include <asm/machvec.h>
+#include <asm/addrspace.h>
 #include <asm/lboxre2.h>
 #include <asm/io.h>
 
@@ -53,7 +54,7 @@ static int __init lboxre2_devices_setup(void)
        unsigned long paddrbase, psize;
 
        /* open I/O area window */
-       paddrbase = virt_to_phys((void*)CONFIG_CF0_BASE_ADDR);
+       paddrbase = virt_to_phys((void*)PA_AREA5_IO);
        psize = PAGE_SIZE;
        prot = PAGE_KERNEL_PCC( 1 , _PAGE_PCC_IO16);
        cf0_io_base = (u32)p3_ioremap(paddrbase, psize, prot.pgprot);
diff --git a/include/asm-sh/lboxre2.h b/include/asm-sh/lboxre2.h
index 6577566..e6d1605 100644
--- a/include/asm-sh/lboxre2.h
+++ b/include/asm-sh/lboxre2.h
@@ -2,8 +2,6 @@
 #define __ASM_SH_LBOXRE2_H
 
 /*
- * linux/include/asm-sh/lbox.h
- *
  * Copyright (C) 2007 Nobuhiro Iwamatsu
  *
  * NTT COMWARE L-BOX RE2 support
@@ -14,11 +12,8 @@
  *
  */
 
-#define CONFIG_CF0_BASE_ADDR   0xb4000000 /* Boot only */
-#define CONFIG_CF1_BASE_ADDR   0xb8000000
-
-#define IRQ_CF1        9       /* CF1 */
-#define IRQ_CF0        10      /* CF0 */
+#define IRQ_CF1                9       /* CF1 */
+#define IRQ_CF0                10      /* CF0 */
 #define IRQ_INTD       11      /* INTD */
 #define IRQ_ETH1       12      /* Ether1 */
 #define IRQ_ETH0       13      /* Ether0 */
-
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