Gitweb:     
http://git.kernel.org/git/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commit;h=c57c2ffb153a99769a15a2ff1729371ddee5601a
Commit:     c57c2ffb153a99769a15a2ff1729371ddee5601a
Parent:     63c3f460cb47c2e06f1726e18534d0e1fe8652a7
Author:     David S. Miller <[EMAIL PROTECTED]>
AuthorDate: Tue May 8 00:43:56 2007 -0700
Committer:  David S. Miller <[EMAIL PROTECTED]>
CommitDate: Tue May 8 16:43:08 2007 -0700

    [SPARC64]: Kill asm-sparc64/pbm.h
    
    Everything it contains can be hidden in pci_impl.h
    
    Signed-off-by: David S. Miller <[EMAIL PROTECTED]>
---
 arch/sparc64/kernel/ebus.c       |    3 +-
 arch/sparc64/kernel/pci.c        |    2 +-
 arch/sparc64/kernel/pci_common.c |    2 +-
 arch/sparc64/kernel/pci_fire.c   |    1 -
 arch/sparc64/kernel/pci_impl.h   |  113 ++++++++++++++++++++++++++++++++
 arch/sparc64/kernel/pci_iommu.c  |    4 +-
 arch/sparc64/kernel/pci_psycho.c |    2 +-
 arch/sparc64/kernel/pci_sabre.c  |    2 +-
 arch/sparc64/kernel/pci_schizo.c |    3 +-
 arch/sparc64/kernel/pci_sun4v.c  |    1 -
 include/asm-sparc64/pbm.h        |  132 --------------------------------------
 11 files changed, 124 insertions(+), 141 deletions(-)

diff --git a/arch/sparc64/kernel/ebus.c b/arch/sparc64/kernel/ebus.c
index 0ace17b..ad55a9b 100644
--- a/arch/sparc64/kernel/ebus.c
+++ b/arch/sparc64/kernel/ebus.c
@@ -13,16 +13,17 @@
 #include <linux/string.h>
 #include <linux/interrupt.h>
 #include <linux/delay.h>
+#include <linux/pci.h>
 
 #include <asm/system.h>
 #include <asm/page.h>
-#include <asm/pbm.h>
 #include <asm/ebus.h>
 #include <asm/oplib.h>
 #include <asm/prom.h>
 #include <asm/of_device.h>
 #include <asm/bpp.h>
 #include <asm/irq.h>
+#include <asm/io.h>
 
 /* EBUS dma library. */
 
diff --git a/arch/sparc64/kernel/pci.c b/arch/sparc64/kernel/pci.c
index ca290d6..d85e1ed 100644
--- a/arch/sparc64/kernel/pci.c
+++ b/arch/sparc64/kernel/pci.c
@@ -14,12 +14,12 @@
 #include <linux/sched.h>
 #include <linux/capability.h>
 #include <linux/errno.h>
+#include <linux/pci.h>
 #include <linux/msi.h>
 #include <linux/irq.h>
 #include <linux/init.h>
 
 #include <asm/uaccess.h>
-#include <asm/pbm.h>
 #include <asm/pgtable.h>
 #include <asm/irq.h>
 #include <asm/ebus.h>
diff --git a/arch/sparc64/kernel/pci_common.c b/arch/sparc64/kernel/pci_common.c
index 8dcc7cc..76faaa8 100644
--- a/arch/sparc64/kernel/pci_common.c
+++ b/arch/sparc64/kernel/pci_common.c
@@ -9,9 +9,9 @@
 #include <linux/pci.h>
 #include <linux/device.h>
 
-#include <asm/pbm.h>
 #include <asm/prom.h>
 #include <asm/of_device.h>
+#include <asm/oplib.h>
 
 #include "pci_impl.h"
 
diff --git a/arch/sparc64/kernel/pci_fire.c b/arch/sparc64/kernel/pci_fire.c
index 5df3130..2e0eb4e 100644
--- a/arch/sparc64/kernel/pci_fire.c
+++ b/arch/sparc64/kernel/pci_fire.c
@@ -7,7 +7,6 @@
 #include <linux/slab.h>
 #include <linux/init.h>
 
-#include <asm/pbm.h>
 #include <asm/oplib.h>
 #include <asm/prom.h>
 
diff --git a/arch/sparc64/kernel/pci_impl.h b/arch/sparc64/kernel/pci_impl.h
index 61505c1..8e38023 100644
--- a/arch/sparc64/kernel/pci_impl.h
+++ b/arch/sparc64/kernel/pci_impl.h
@@ -8,8 +8,119 @@
 
 #include <linux/types.h>
 #include <linux/spinlock.h>
+#include <linux/pci.h>
+#include <linux/msi.h>
 #include <asm/io.h>
 #include <asm/prom.h>
+#include <asm/iommu.h>
+
+/* The abstraction used here is that there are PCI controllers,
+ * each with one (Sabre) or two (PSYCHO/SCHIZO) PCI bus modules
+ * underneath.  Each PCI bus module uses an IOMMU (shared by both
+ * PBMs of a controller, or per-PBM), and if a streaming buffer
+ * is present, each PCI bus module has it's own. (ie. the IOMMU
+ * might be shared between PBMs, the STC is never shared)
+ * Furthermore, each PCI bus module controls it's own autonomous
+ * PCI bus.
+ */
+
+#define PCI_STC_FLUSHFLAG_INIT(STC) \
+       (*((STC)->strbuf_flushflag) = 0UL)
+#define PCI_STC_FLUSHFLAG_SET(STC) \
+       (*((STC)->strbuf_flushflag) != 0UL)
+
+struct pci_controller_info;
+
+struct pci_pbm_info {
+       struct pci_pbm_info             *next;
+       int                             index;
+
+       /* PCI controller we sit under. */
+       struct pci_controller_info      *parent;
+
+       /* Physical address base of controller registers. */
+       unsigned long                   controller_regs;
+
+       /* Physical address base of PBM registers. */
+       unsigned long                   pbm_regs;
+
+       /* Physical address of DMA sync register, if any.  */
+       unsigned long                   sync_reg;
+
+       /* Opaque 32-bit system bus Port ID. */
+       u32                             portid;
+
+       /* Opaque 32-bit handle used for hypervisor calls.  */
+       u32                             devhandle;
+
+       /* Chipset version information. */
+       int                             chip_type;
+#define PBM_CHIP_TYPE_SABRE            1
+#define PBM_CHIP_TYPE_PSYCHO           2
+#define PBM_CHIP_TYPE_SCHIZO           3
+#define PBM_CHIP_TYPE_SCHIZO_PLUS      4
+#define PBM_CHIP_TYPE_TOMATILLO                5
+       int                             chip_version;
+       int                             chip_revision;
+
+       /* Name used for top-level resources. */
+       char                            *name;
+
+       /* OBP specific information. */
+       struct device_node              *prom_node;
+       u64                             ino_bitmap;
+
+       /* PBM I/O and Memory space resources. */
+       struct resource                 io_space;
+       struct resource                 mem_space;
+
+       /* Base of PCI Config space, can be per-PBM or shared. */
+       unsigned long                   config_space;
+
+       /* State of 66MHz capabilities on this PBM. */
+       int                             is_66mhz_capable;
+       int                             all_devs_66mhz;
+
+#ifdef CONFIG_PCI_MSI
+       /* MSI info.  */
+       u32                             msiq_num;
+       u32                             msiq_ent_count;
+       u32                             msiq_first;
+       u32                             msiq_first_devino;
+       u32                             msi_num;
+       u32                             msi_first;
+       u32                             msi_data_mask;
+       u32                             msix_data_width;
+       u64                             msi32_start;
+       u64                             msi64_start;
+       u32                             msi32_len;
+       u32                             msi64_len;
+       void                            *msi_queues;
+       unsigned long                   *msi_bitmap;
+       int (*setup_msi_irq)(unsigned int *virt_irq_p, struct pci_dev *pdev,
+                            struct msi_desc *entry);
+       void (*teardown_msi_irq)(unsigned int virt_irq, struct pci_dev *pdev);
+#endif /* !(CONFIG_PCI_MSI) */
+
+       /* This PBM's streaming buffer. */
+       struct strbuf                   stc;
+
+       /* IOMMU state, potentially shared by both PBM segments. */
+       struct iommu                    *iommu;
+
+       /* Now things for the actual PCI bus probes. */
+       unsigned int                    pci_first_busno;
+       unsigned int                    pci_last_busno;
+       struct pci_bus                  *pci_bus;
+       void (*scan_bus)(struct pci_pbm_info *);
+       struct pci_ops                  *pci_ops;
+};
+
+struct pci_controller_info {
+       /* The PCI bus modules controlled by us. */
+       struct pci_pbm_info             pbm_A;
+       struct pci_pbm_info             pbm_B;
+};
 
 extern struct pci_pbm_info *pci_pbm_root;
 extern unsigned long pci_memspace_mask;
@@ -17,6 +128,8 @@ extern unsigned long pci_memspace_mask;
 extern int pci_num_pbms;
 
 /* PCI bus scanning and fixup support. */
+extern void pci_iommu_table_init(struct iommu *iommu, int tsbsize,
+                                u32 dma_offset, u32 dma_addr_mask);
 extern void pci_get_pbm_props(struct pci_pbm_info *pbm);
 extern struct pci_bus *pci_scan_one_pbm(struct pci_pbm_info *pbm);
 extern void pci_determine_mem_io_space(struct pci_pbm_info *pbm);
diff --git a/arch/sparc64/kernel/pci_iommu.c b/arch/sparc64/kernel/pci_iommu.c
index 9e405cb..dfd6f9f 100644
--- a/arch/sparc64/kernel/pci_iommu.c
+++ b/arch/sparc64/kernel/pci_iommu.c
@@ -8,10 +8,12 @@
 #include <linux/sched.h>
 #include <linux/mm.h>
 #include <linux/delay.h>
+#include <linux/pci.h>
 
-#include <asm/pbm.h>
+#include <asm/oplib.h>
 
 #include "iommu_common.h"
+#include "pci_impl.h"
 
 #define PCI_STC_CTXMATCH_ADDR(STC, CTX)        \
        ((STC)->strbuf_ctxmatch_base + ((CTX) << 3))
diff --git a/arch/sparc64/kernel/pci_psycho.c b/arch/sparc64/kernel/pci_psycho.c
index 8ef8083..401e5df 100644
--- a/arch/sparc64/kernel/pci_psycho.c
+++ b/arch/sparc64/kernel/pci_psycho.c
@@ -12,12 +12,12 @@
 #include <linux/slab.h>
 #include <linux/interrupt.h>
 
-#include <asm/pbm.h>
 #include <asm/iommu.h>
 #include <asm/irq.h>
 #include <asm/starfire.h>
 #include <asm/prom.h>
 #include <asm/of_device.h>
+#include <asm/oplib.h>
 
 #include "pci_impl.h"
 #include "iommu_common.h"
diff --git a/arch/sparc64/kernel/pci_sabre.c b/arch/sparc64/kernel/pci_sabre.c
index 733ab36..863308c 100644
--- a/arch/sparc64/kernel/pci_sabre.c
+++ b/arch/sparc64/kernel/pci_sabre.c
@@ -13,12 +13,12 @@
 #include <linux/interrupt.h>
 
 #include <asm/apb.h>
-#include <asm/pbm.h>
 #include <asm/iommu.h>
 #include <asm/irq.h>
 #include <asm/smp.h>
 #include <asm/oplib.h>
 #include <asm/prom.h>
+#include <asm/of_device.h>
 
 #include "pci_impl.h"
 #include "iommu_common.h"
diff --git a/arch/sparc64/kernel/pci_schizo.c b/arch/sparc64/kernel/pci_schizo.c
index 72743ac..312f3e4 100644
--- a/arch/sparc64/kernel/pci_schizo.c
+++ b/arch/sparc64/kernel/pci_schizo.c
@@ -10,12 +10,13 @@
 #include <linux/slab.h>
 #include <linux/interrupt.h>
 
-#include <asm/pbm.h>
 #include <asm/iommu.h>
 #include <asm/irq.h>
 #include <asm/upa.h>
 #include <asm/pstate.h>
 #include <asm/prom.h>
+#include <asm/of_device.h>
+#include <asm/oplib.h>
 
 #include "pci_impl.h"
 #include "iommu_common.h"
diff --git a/arch/sparc64/kernel/pci_sun4v.c b/arch/sparc64/kernel/pci_sun4v.c
index ce46b04..0c76a88 100644
--- a/arch/sparc64/kernel/pci_sun4v.c
+++ b/arch/sparc64/kernel/pci_sun4v.c
@@ -13,7 +13,6 @@
 #include <linux/irq.h>
 #include <linux/msi.h>
 
-#include <asm/pbm.h>
 #include <asm/iommu.h>
 #include <asm/irq.h>
 #include <asm/upa.h>
diff --git a/include/asm-sparc64/pbm.h b/include/asm-sparc64/pbm.h
deleted file mode 100644
index d99e046..0000000
--- a/include/asm-sparc64/pbm.h
+++ /dev/null
@@ -1,132 +0,0 @@
-/* pbm.h: UltraSparc PCI controller software state.
- *
- * Copyright (C) 1997, 1998, 1999, 2007 David S. Miller ([EMAIL PROTECTED])
- */
-
-#ifndef __SPARC64_PBM_H
-#define __SPARC64_PBM_H
-
-#include <linux/types.h>
-#include <linux/pci.h>
-#include <linux/ioport.h>
-#include <linux/spinlock.h>
-#include <linux/msi.h>
-
-#include <asm/io.h>
-#include <asm/page.h>
-#include <asm/oplib.h>
-#include <asm/prom.h>
-#include <asm/of_device.h>
-#include <asm/iommu.h>
-
-/* The abstraction used here is that there are PCI controllers,
- * each with one (Sabre) or two (PSYCHO/SCHIZO) PCI bus modules
- * underneath.  Each PCI bus module uses an IOMMU (shared by both
- * PBMs of a controller, or per-PBM), and if a streaming buffer
- * is present, each PCI bus module has it's own. (ie. the IOMMU
- * might be shared between PBMs, the STC is never shared)
- * Furthermore, each PCI bus module controls it's own autonomous
- * PCI bus.
- */
-
-extern void pci_iommu_table_init(struct iommu *iommu, int tsbsize, u32 
dma_offset, u32 dma_addr_mask);
-
-#define PCI_STC_FLUSHFLAG_INIT(STC) \
-       (*((STC)->strbuf_flushflag) = 0UL)
-#define PCI_STC_FLUSHFLAG_SET(STC) \
-       (*((STC)->strbuf_flushflag) != 0UL)
-
-struct pci_controller_info;
-
-struct pci_pbm_info {
-       struct pci_pbm_info             *next;
-       int                             index;
-
-       /* PCI controller we sit under. */
-       struct pci_controller_info      *parent;
-
-       /* Physical address base of controller registers. */
-       unsigned long                   controller_regs;
-
-       /* Physical address base of PBM registers. */
-       unsigned long                   pbm_regs;
-
-       /* Physical address of DMA sync register, if any.  */
-       unsigned long                   sync_reg;
-
-       /* Opaque 32-bit system bus Port ID. */
-       u32                             portid;
-
-       /* Opaque 32-bit handle used for hypervisor calls.  */
-       u32                             devhandle;
-
-       /* Chipset version information. */
-       int                             chip_type;
-#define PBM_CHIP_TYPE_SABRE            1
-#define PBM_CHIP_TYPE_PSYCHO           2
-#define PBM_CHIP_TYPE_SCHIZO           3
-#define PBM_CHIP_TYPE_SCHIZO_PLUS      4
-#define PBM_CHIP_TYPE_TOMATILLO                5
-       int                             chip_version;
-       int                             chip_revision;
-
-       /* Name used for top-level resources. */
-       char                            *name;
-
-       /* OBP specific information. */
-       struct device_node              *prom_node;
-       u64                             ino_bitmap;
-
-       /* PBM I/O and Memory space resources. */
-       struct resource                 io_space;
-       struct resource                 mem_space;
-
-       /* Base of PCI Config space, can be per-PBM or shared. */
-       unsigned long                   config_space;
-
-       /* State of 66MHz capabilities on this PBM. */
-       int                             is_66mhz_capable;
-       int                             all_devs_66mhz;
-
-#ifdef CONFIG_PCI_MSI
-       /* MSI info.  */
-       u32                             msiq_num;
-       u32                             msiq_ent_count;
-       u32                             msiq_first;
-       u32                             msiq_first_devino;
-       u32                             msi_num;
-       u32                             msi_first;
-       u32                             msi_data_mask;
-       u32                             msix_data_width;
-       u64                             msi32_start;
-       u64                             msi64_start;
-       u32                             msi32_len;
-       u32                             msi64_len;
-       void                            *msi_queues;
-       unsigned long                   *msi_bitmap;
-       int (*setup_msi_irq)(unsigned int *virt_irq_p, struct pci_dev *pdev,
-                            struct msi_desc *entry);
-       void (*teardown_msi_irq)(unsigned int virt_irq, struct pci_dev *pdev);
-#endif /* !(CONFIG_PCI_MSI) */
-
-       /* This PBM's streaming buffer. */
-       struct strbuf                   stc;
-
-       /* IOMMU state, potentially shared by both PBM segments. */
-       struct iommu                    *iommu;
-
-       /* Now things for the actual PCI bus probes. */
-       unsigned int                    pci_first_busno;
-       unsigned int                    pci_last_busno;
-       struct pci_bus                  *pci_bus;
-       void (*scan_bus)(struct pci_pbm_info *);
-       struct pci_ops                  *pci_ops;
-};
-
-struct pci_controller_info {
-       /* The PCI bus modules controlled by us. */
-       struct pci_pbm_info             pbm_A;
-       struct pci_pbm_info             pbm_B;
-};
-
-#endif /* !(__SPARC64_PBM_H) */
-
To unsubscribe from this list: send the line "unsubscribe git-commits-head" in
the body of a message to [EMAIL PROTECTED]
More majordomo info at  http://vger.kernel.org/majordomo-info.html

Reply via email to