Gitweb:     
http://git.kernel.org/git/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commit;h=b85fe92766dfc0c4e803cb0cead4c780cd0c02f9
Commit:     b85fe92766dfc0c4e803cb0cead4c780cd0c02f9
Parent:     8eef3896b352a8760ab04293174444da4e8c8127
Author:     Andrew Victor <[EMAIL PROTECTED]>
AuthorDate: Tue May 8 07:51:23 2007 +0100
Committer:  Russell King <[EMAIL PROTECTED]>
CommitDate: Tue May 8 20:45:21 2007 +0100

    [ARM] 4363/1: AT91: Remove legacy PIO definitions
    
    Remove the legacy PIO pin definitions for the AT91 processors.
    The standard (and portable between the different AT91 processors) method
    is to use the AT91_PIN_* defines and the GPIO API.
    
    Signed-off-by: Andrew Victor <[EMAIL PROTECTED]>
    Signed-off-by: Russell King <[EMAIL PROTECTED]>
---
 include/asm-arm/arch-at91/at91rm9200.h  |  181 -----------------------------
 include/asm-arm/arch-at91/at91sam9260.h |    9 --
 include/asm-arm/arch-at91/at91sam9261.h |  191 -------------------------------
 include/asm-arm/arch-at91/at91sam9263.h |    8 --
 4 files changed, 0 insertions(+), 389 deletions(-)

diff --git a/include/asm-arm/arch-at91/at91rm9200.h 
b/include/asm-arm/arch-at91/at91rm9200.h
index a12ac8a..802891a 100644
--- a/include/asm-arm/arch-at91/at91rm9200.h
+++ b/include/asm-arm/arch-at91/at91rm9200.h
@@ -107,185 +107,4 @@
 #define AT91RM9200_UHP_BASE    0x00300000      /* USB Host controller */
 
 
-#if 0
-/*
- * PIO pin definitions (peripheral A/B multiplexing).
- */
-#define AT91_PA0_MISO          (1 <<  0)       /* A: SPI Master-In Slave-Out */
-#define AT91_PA0_PCK3          (1 <<  0)       /* B: PMC Programmable Clock 
Output 3 */
-#define AT91_PA1_MOSI          (1 <<  1)       /* A: SPI Master-Out Slave-In */
-#define AT91_PA1_PCK0          (1 <<  1)       /* B: PMC Programmable Clock 
Output 0 */
-#define AT91_PA2_SPCK          (1 <<  2)       /* A: SPI Serial Clock */
-#define AT91_PA2_IRQ4          (1 <<  2)       /* B: External Interrupt 4 */
-#define AT91_PA3_NPCS0         (1 <<  3)       /* A: SPI Peripheral Chip 
Select 0 */
-#define AT91_PA3_IRQ5          (1 <<  3)       /* B: External Interrupt 5 */
-#define AT91_PA4_NPCS1         (1 <<  4)       /* A: SPI Peripheral Chip 
Select 1 */
-#define AT91_PA4_PCK1          (1 <<  4)       /* B: PMC Programmable Clock 
Output 1 */
-#define AT91_PA5_NPCS2         (1 <<  5)       /* A: SPI Peripheral Chip 
Select 2 */
-#define AT91_PA5_TXD3          (1 <<  5)       /* B: USART Transmit Data 3 */
-#define AT91_PA6_NPCS3         (1 <<  6)       /* A: SPI Peripheral Chip 
Select 3 */
-#define AT91_PA6_RXD3          (1 <<  6)       /* B: USART Receive Data 3 */
-#define AT91_PA7_ETXCK_EREFCK  (1 <<  7)       /* A: Ethernet Reference Clock 
/ Transmit Clock */
-#define AT91_PA7_PCK2          (1 <<  7)       /* B: PMC Programmable Clock 
Output 2 */
-#define AT91_PA8_ETXEN         (1 <<  8)       /* A: Ethernet Transmit Enable 
*/
-#define AT91_PA8_MCCDB         (1 <<  8)       /* B: MMC Multimedia Card B 
Command */
-#define AT91_PA9_ETX0          (1 <<  9)       /* A: Ethernet Transmit Data 0 
*/
-#define AT91_PA9_MCDB0         (1 <<  9)       /* B: MMC Multimedia Card B 
Data 0 */
-#define AT91_PA10_ETX1         (1 << 10)       /* A: Ethernet Transmit Data 1 
*/
-#define AT91_PA10_MCDB1                (1 << 10)       /* B: MMC Multimedia 
Card B Data 1 */
-#define AT91_PA11_ECRS_ECRSDV  (1 << 11)       /* A: Ethernet Carrier Sense / 
Data Valid */
-#define AT91_PA11_MCDB2                (1 << 11)       /* B: MMC Multimedia 
Card B Data 2 */
-#define AT91_PA12_ERX0         (1 << 12)       /* A: Ethernet Receive Data 0 */
-#define AT91_PA12_MCDB3                (1 << 12)       /* B: MMC Multimedia 
Card B Data 3 */
-#define AT91_PA13_ERX1         (1 << 13)       /* A: Ethernet Receive Data 1 */
-#define AT91_PA13_TCLK0                (1 << 13)       /* B: TC External Clock 
Input 0 */
-#define AT91_PA14_ERXER                (1 << 14)       /* A: Ethernet Receive 
Error */
-#define AT91_PA14_TCLK1                (1 << 14)       /* B: TC External Clock 
Input 1 */
-#define AT91_PA15_EMDC         (1 << 15)       /* A: Ethernet Management Data 
Clock */
-#define AT91_PA15_TCLK2                (1 << 15)       /* B: TC External Clock 
Input 2 */
-#define AT91_PA16_EMDIO                (1 << 16)       /* A: Ethernet 
Management Data I/O */
-#define AT91_PA16_IRQ6         (1 << 16)       /* B: External Interrupt 6 */
-#define AT91_PA17_TXD0         (1 << 17)       /* A: USART Transmit Data 0 */
-#define AT91_PA17_TIOA0                (1 << 17)       /* B: TC I/O Line A 0 */
-#define AT91_PA18_RXD0         (1 << 18)       /* A: USART Receive Data 0 */
-#define AT91_PA18_TIOB0                (1 << 18)       /* B: TC I/O Line B 0 */
-#define AT91_PA19_SCK0         (1 << 19)       /* A: USART Serial Clock 0 */
-#define AT91_PA19_TIOA1                (1 << 19)       /* B: TC I/O Line A 1 */
-#define AT91_PA20_CTS0         (1 << 20)       /* A: USART Clear To Send 0 */
-#define AT91_PA20_TIOB1                (1 << 20)       /* B: TC I/O Line B 1 */
-#define AT91_PA21_RTS0         (1 << 21)       /* A: USART Ready To Send 0 */
-#define AT91_PA21_TIOA2                (1 << 21)       /* B: TC I/O Line A 2 */
-#define AT91_PA22_RXD2         (1 << 22)       /* A: USART Receive Data 2 */
-#define AT91_PA22_TIOB2                (1 << 22)       /* B: TC I/O Line B 2 */
-#define AT91_PA23_TXD2         (1 << 23)       /* A: USART Transmit Data 2 */
-#define AT91_PA23_IRQ3         (1 << 23)       /* B: External Interrupt 3 */
-#define AT91_PA24_SCK2         (1 << 24)       /* A: USART Serial Clock 2 */
-#define AT91_PA24_PCK1         (1 << 24)       /* B: PMC Programmable Clock 
Output 1 */
-#define AT91_PA25_TWD          (1 << 25)       /* A: TWI Two-wire Serial Data 
*/
-#define AT91_PA25_IRQ2         (1 << 25)       /* B: External Interrupt 2 */
-#define AT91_PA26_TWCK         (1 << 26)       /* A: TWI Two-wire Serial Clock 
*/
-#define AT91_PA26_IRQ1         (1 << 26)       /* B: External Interrupt 1 */
-#define AT91_PA27_MCCK         (1 << 27)       /* A: MMC Multimedia Card Clock 
*/
-#define AT91_PA27_TCLK3                (1 << 27)       /* B: TC External Clock 
Input 3 */
-#define AT91_PA28_MCCDA                (1 << 28)       /* A: MMC Multimedia 
Card A Command */
-#define AT91_PA28_TCLK4                (1 << 28)       /* B: TC External Clock 
Input 4 */
-#define AT91_PA29_MCDA0                (1 << 29)       /* A: MMC Multimedia 
Card A Data 0 */
-#define AT91_PA29_TCLK5                (1 << 29)       /* B: TC External Clock 
Input 5 */
-#define AT91_PA30_DRXD         (1 << 30)       /* A: DBGU Receive Data */
-#define AT91_PA30_CTS2         (1 << 30)       /* B: USART Clear To Send 2 */
-#define AT91_PA31_DTXD         (1 << 31)       /* A: DBGU Transmit Data */
-#define AT91_PA31_RTS2         (1 << 31)       /* B: USART Ready To Send 2 */
-
-#define AT91_PB0_TF0           (1 <<  0)       /* A: SSC Transmit Frame Sync 0 
*/
-#define AT91_PB0_RTS3          (1 <<  0)       /* B: USART Ready To Send 3 */
-#define AT91_PB1_TK0           (1 <<  1)       /* A: SSC Transmit Clock 0 */
-#define AT91_PB1_CTS3          (1 <<  1)       /* B: USART Clear To Send 3 */
-#define AT91_PB2_TD0           (1 <<  2)       /* A: SSC Transmit Data 0 */
-#define AT91_PB2_SCK3          (1 <<  2)       /* B: USART Serial Clock 3 */
-#define AT91_PB3_RD0           (1 <<  3)       /* A: SSC Receive Data 0 */
-#define AT91_PB3_MCDA1         (1 <<  3)       /* B: MMC Multimedia Card A 
Data 1 */
-#define AT91_PB4_RK0           (1 <<  4)       /* A: SSC Receive Clock 0 */
-#define AT91_PB4_MCDA2         (1 <<  4)       /* B: MMC Multimedia Card A 
Data 2 */
-#define AT91_PB5_RF0           (1 <<  5)       /* A: SSC Receive Frame Sync 0 
*/
-#define AT91_PB5_MCDA3         (1 <<  5)       /* B: MMC Multimedia Card A 
Data 3 */
-#define AT91_PB6_TF1           (1 <<  6)       /* A: SSC Transmit Frame Sync 1 
*/
-#define AT91_PB6_TIOA3         (1 <<  6)       /* B: TC I/O Line A 3 */
-#define AT91_PB7_TK1           (1 <<  7)       /* A: SSC Transmit Clock 1 */
-#define AT91_PB7_TIOB3         (1 <<  7)       /* B: TC I/O Line B 3 */
-#define AT91_PB8_TD1           (1 <<  8)       /* A: SSC Transmit Data 1 */
-#define AT91_PB8_TIOA4         (1 <<  8)       /* B: TC I/O Line A 4 */
-#define AT91_PB9_RD1           (1 <<  9)       /* A: SSC Receive Data 1 */
-#define AT91_PB9_TIOB4         (1 <<  9)       /* B: TC I/O Line B 4 */
-#define AT91_PB10_RK1          (1 << 10)       /* A: SSC Receive Clock 1 */
-#define AT91_PB10_TIOA5                (1 << 10)       /* B: TC I/O Line A 5 */
-#define AT91_PB11_RF1          (1 << 11)       /* A: SSC Receive Frame Sync 1 
*/
-#define AT91_PB11_TIOB5                (1 << 11)       /* B: TC I/O Line B 5 */
-#define AT91_PB12_TF2          (1 << 12)       /* A: SSC Transmit Frame Sync 2 
*/
-#define AT91_PB12_ETX2         (1 << 12)       /* B: Ethernet Transmit Data 2 
*/
-#define AT91_PB13_TK2          (1 << 13)       /* A: SSC Transmit Clock 3 */
-#define AT91_PB13_ETX3         (1 << 13)       /* B: Ethernet Transmit Data 3 
*/
-#define AT91_PB14_TD2          (1 << 14)       /* A: SSC Transmit Data 2 */
-#define AT91_PB14_ETXER                (1 << 14)       /* B: Ethernet Transmit 
Coding Error */
-#define AT91_PB15_RD2          (1 << 15)       /* A: SSC Receive Data 2 */
-#define AT91_PB15_ERX2         (1 << 15)       /* B: Ethernet Receive Data 2 */
-#define AT91_PB16_RK2          (1 << 16)       /* A: SSC Receive Clock 2 */
-#define AT91_PB16_ERX3         (1 << 16)       /* B: Ethernet Receive Data 3 */
-#define AT91_PB17_RF2          (1 << 17)       /* A: SSC Receive Frame Sync 2 
*/
-#define AT91_PB17_ERXDV                (1 << 17)       /* B: Ethernet Receive 
Data Valid */
-#define AT91_PB18_RI1          (1 << 18)       /* A: USART Ring Indicator 1 */
-#define AT91_PB18_ECOL         (1 << 18)       /* B: Ethernet Collision 
Detected */
-#define AT91_PB19_DTR1         (1 << 19)       /* A: USART Data Terminal Ready 
1 */
-#define AT91_PB19_ERXCK                (1 << 19)       /* B: Ethernet Receive 
Clock */
-#define AT91_PB20_TXD1         (1 << 20)       /* A: USART Transmit Data 1 */
-#define AT91_PB21_RXD1         (1 << 21)       /* A: USART Receive Data 1 */
-#define AT91_PB22_SCK1         (1 << 22)       /* A: USART Serial Clock 1 */
-#define AT91_PB23_DCD1         (1 << 23)       /* A: USART Data Carrier Detect 
1 */
-#define AT91_PB24_CTS1         (1 << 24)       /* A: USART Clear To Send 1 */
-#define AT91_PB25_DSR1         (1 << 25)       /* A: USART Data Set Ready 1 */
-#define AT91_PB25_EF100                (1 << 25)       /* B: Ethernet Force 
100 Mbit */
-#define AT91_PB26_RTS1         (1 << 26)       /* A: USART Ready To Send 1 */
-#define AT91_PB27_PCK0         (1 << 27)       /* B: PMC Programmable Clock 
Output 0 */
-#define AT91_PB28_FIQ          (1 << 28)       /* A: Fast Interrupt */
-#define AT91_PB29_IRQ0         (1 << 29)       /* A: External Interrupt 0 */
-
-#define AT91_PC0_BFCK          (1 <<  0)       /* A: Burst Flash Clock */
-#define AT91_PC1_BFRDY_SMOE    (1 <<  1)       /* A: Burst Flash Ready / 
SmartMedia Output Enable */
-#define AT91_PC2_BFAVD         (1 <<  2)       /* A: Burst Flash Address Valid 
*/
-#define AT91_PC3_BFBAA_SMWE    (1 <<  3)       /* A: Burst Flash Address 
Advance / SmartMedia Write Enable */
-#define AT91_PC4_BFOE          (1 <<  4)       /* A: Burst Flash Output Enable 
*/
-#define AT91_PC5_BFWE          (1 <<  5)       /* A: Burst Flash Write Enable 
*/
-#define AT91_PC6_NWAIT         (1 <<  6)       /* A: SMC Wait Signal */
-#define AT91_PC7_A23           (1 <<  7)       /* A: Address Bus 23 */
-#define AT91_PC8_A24           (1 <<  8)       /* A: Address Bus 24 */
-#define AT91_PC9_A25_CFRNW     (1 <<  9)       /* A: Address Bus 25 / Compact 
Flash Read Not Write */
-#define AT91_PC10_NCS4_CFCS    (1 << 10)       /* A: SMC Chip Select 4 / 
Compact Flash Chip Select */
-#define AT91_PC11_NCS5_CFCE1   (1 << 11)       /* A: SMC Chip Select 5 / 
Compact Flash Chip Enable 1 */
-#define AT91_PC12_NCS6_CFCE2   (1 << 12)       /* A: SMC Chip Select 6 / 
Compact Flash Chip Enable 2 */
-#define AT91_PC13_NCS7         (1 << 13)       /* A: Chip Select 7 */
-
-#define AT91_PD0_ETX0          (1 <<  0)       /* A: Ethernet Transmit Data 0 
*/
-#define AT91_PD1_ETX1          (1 <<  1)       /* A: Ethernet Transmit Data 1 
*/
-#define AT91_PD2_ETX2          (1 <<  2)       /* A: Ethernet Transmit Data 2 
*/
-#define AT91_PD3_ETX3          (1 <<  3)       /* A: Ethernet Transmit Data 3 
*/
-#define AT91_PD4_ETXEN         (1 <<  4)       /* A: Ethernet Transmit Enable 
*/
-#define AT91_PD5_ETXER         (1 <<  5)       /* A: Ethernet Transmit Coding 
Error */
-#define AT91_PD6_DTXD          (1 <<  6)       /* A: DBGU Transmit Data */
-#define AT91_PD7_PCK0          (1 <<  7)       /* A: PMC Programmable Clock 
Output 0 */
-#define AT91_PD7_TSYNC         (1 <<  7)       /* B: ETM Trace Synchronization 
Signal */
-#define AT91_PD8_PCK1          (1 <<  8)       /* A: PMC Programmable Clock 
Output 1 */
-#define AT91_PD8_TCLK          (1 <<  8)       /* B: ETM Trace Clock */
-#define AT91_PD9_PCK2          (1 <<  9)       /* A: PMC Programmable Clock 
Output 2 */
-#define AT91_PD9_TPS0          (1 <<  9)       /* B: ETM Trace ARM Pipeline 
Status 0 */
-#define AT91_PD10_PCK3         (1 << 10)       /* A: PMC Programmable Clock 
Output 3 */
-#define AT91_PD10_TPS1         (1 << 10)       /* B: ETM Trace ARM Pipeline 
Status 1 */
-#define AT91_PD11_TPS2         (1 << 11)       /* B: ETM Trace ARM Pipeline 
Status 2 */
-#define AT91_PD12_TPK0         (1 << 12)       /* B: ETM Trace Packet Port 0 */
-#define AT91_PD13_TPK1         (1 << 13)       /* B: ETM Trace Packet Port 1 */
-#define AT91_PD14_TPK2         (1 << 14)       /* B: ETM Trace Packet Port 2 */
-#define AT91_PD15_TD0          (1 << 15)       /* A: SSC Transmit Data 0 */
-#define AT91_PD15_TPK3         (1 << 15)       /* B: ETM Trace Packet Port 3 */
-#define AT91_PD16_TD1          (1 << 16)       /* A: SSC Transmit Data 1 */
-#define AT91_PD16_TPK4         (1 << 16)       /* B: ETM Trace Packet Port 4 */
-#define AT91_PD17_TD2          (1 << 17)       /* A: SSC Transmit Data 2 */
-#define AT91_PD17_TPK5         (1 << 17)       /* B: ETM Trace Packet Port 5 */
-#define AT91_PD18_NPCS1                (1 << 18)       /* A: SPI Peripheral 
Chip Select 1 */
-#define AT91_PD18_TPK6         (1 << 18)       /* B: ETM Trace Packet Port 6 */
-#define AT91_PD19_NPCS2                (1 << 19)       /* A: SPI Peripheral 
Chip Select 2 */
-#define AT91_PD19_TPK7         (1 << 19)       /* B: ETM Trace Packet Port 7 */
-#define AT91_PD20_NPCS3                (1 << 20)       /* A: SPI Peripheral 
Chip Select 3 */
-#define AT91_PD20_TPK8         (1 << 20)       /* B: ETM Trace Packet Port 8 */
-#define AT91_PD21_RTS0         (1 << 21)       /* A: USART Ready To Send 0 */
-#define AT91_PD21_TPK9         (1 << 21)       /* B: ETM Trace Packet Port 9 */
-#define AT91_PD22_RTS1         (1 << 22)       /* A: USART Ready To Send 1 */
-#define AT91_PD22_TPK10                (1 << 22)       /* B: ETM Trace Packet 
Port 10 */
-#define AT91_PD23_RTS2         (1 << 23)       /* A: USART Ready To Send 2 */
-#define AT91_PD23_TPK11                (1 << 23)       /* B: ETM Trace Packet 
Port 11 */
-#define AT91_PD24_RTS3         (1 << 24)       /* A: USART Ready To Send 3 */
-#define AT91_PD24_TPK12                (1 << 24)       /* B: ETM Trace Packet 
Port 12 */
-#define AT91_PD25_DTR1         (1 << 25)       /* A: USART Data Terminal Ready 
1 */
-#define AT91_PD25_TPK13                (1 << 25)       /* B: ETM Trace Packet 
Port 13 */
-#define AT91_PD26_TPK14                (1 << 26)       /* B: ETM Trace Packet 
Port 14 */
-#define AT91_PD27_TPK15                (1 << 27)       /* B: ETM Trace Packet 
Port 15 */
-#endif
-
 #endif
diff --git a/include/asm-arm/arch-at91/at91sam9260.h 
b/include/asm-arm/arch-at91/at91sam9260.h
index 2cadebc..0427f86 100644
--- a/include/asm-arm/arch-at91/at91sam9260.h
+++ b/include/asm-arm/arch-at91/at91sam9260.h
@@ -117,13 +117,4 @@
 #define AT91SAM9XE_SRAM_BASE   0x00300000      /* Internal SRAM base address */
 
 
-#if 0
-/*
- * PIO pin definitions (peripheral A/B multiplexing).
- */
-
-// TODO: Add
-
-#endif
-
 #endif
diff --git a/include/asm-arm/arch-at91/at91sam9261.h 
b/include/asm-arm/arch-at91/at91sam9261.h
index 01b58ff..9eb4595 100644
--- a/include/asm-arm/arch-at91/at91sam9261.h
+++ b/include/asm-arm/arch-at91/at91sam9261.h
@@ -98,195 +98,4 @@
 #define AT91SAM9261_LCDC_BASE  0x00600000      /* LDC controller */
 
 
-#if 0
-/*
- * PIO pin definitions (peripheral A/B multiplexing).
- */
-#define AT91_PA0_SPI0_MISO     (1 <<  0)       /* A: SPI0 Master In Slave */
-#define AT91_PA0_MCDA0         (1 <<  0)       /* B: Multimedia Card A Data 0 
*/
-#define AT91_PA1_SPI0_MOSI     (1 <<  1)       /* A: SPI0 Master Out Slave */
-#define AT91_PA1_MCCDA         (1 <<  1)       /* B: Multimedia Card A Command 
*/
-#define AT91_PA2_SPI0_SPCK     (1 <<  2)       /* A: SPI0 Serial Clock */
-#define AT91_PA2_MCCK          (1 <<  2)       /* B: Multimedia Card Clock */
-#define AT91_PA3_SPI0_NPCS0    (1 <<  3)       /* A: SPI0 Peripheral Chip 
Select 0 */
-#define AT91_PA4_SPI0_NPCS1    (1 <<  4)       /* A: SPI0 Peripheral Chip 
Select 1 */
-#define AT91_PA4_MCDA1         (1 <<  4)       /* B: Multimedia Card A Data 1 
*/
-#define AT91_PA5_SPI0_NPCS2    (1 <<  5)       /* A: SPI0 Peripheral Chip 
Select 2 */
-#define AT91_PA5_MCDA2         (1 <<  5)       /* B: Multimedia Card A Data 2 
*/
-#define AT91_PA6_SPI0_NPCS3    (1 <<  6)       /* A: SPI0 Peripheral Chip 
Select 3 */
-#define AT91_PA6_MCDA3         (1 <<  6)       /* B: Multimedia Card A Data 3 
*/
-#define AT91_PA7_TWD           (1 <<  7)       /* A: TWI Two-wire Serial Data 
*/
-#define AT91_PA7_PCK0          (1 <<  7)       /* B: PMC Programmable clock 
Output 0 */
-#define AT91_PA8_TWCK          (1 <<  8)       /* A: TWI Two-wire Serial Clock 
*/
-#define AT91_PA8_PCK1          (1 <<  8)       /* B: PMC Programmable clock 
Output 1 */
-#define AT91_PA9_DRXD          (1 <<  9)       /* A: DBGU Debug Receive Data */
-#define AT91_PA9_PCK2          (1 <<  9)       /* B: PMC Programmable clock 
Output 2 */
-#define AT91_PA10_DTXD         (1 << 10)       /* A: DBGU Debug Transmit Data 
*/
-#define AT91_PA10_PCK3         (1 << 10)       /* B: PMC Programmable clock 
Output 3 */
-#define AT91_PA11_TSYNC                (1 << 11)       /* A: Trace 
Synchronization Signal */
-#define AT91_PA11_SCK1         (1 << 11)       /* B: USART1 Serial Clock */
-#define AT91_PA12_TCLK         (1 << 12)       /* A: Trace Clock */
-#define AT91_PA12_RTS1         (1 << 12)       /* B: USART1 Ready To Send */
-#define AT91_PA13_TPS0         (1 << 13)       /* A: Trace ARM Pipeline Status 
0 */
-#define AT91_PA13_CTS1         (1 << 13)       /* B: USART1 Clear To Send */
-#define AT91_PA14_TPS1         (1 << 14)       /* A: Trace ARM Pipeline Status 
1 */
-#define AT91_PA14_SCK2         (1 << 14)       /* B: USART2 Serial Clock */
-#define AT91_PA15_TPS2         (1 << 15)       /* A: Trace ARM Pipeline Status 
2 */
-#define AT91_PA15_RTS2         (1 << 15)       /* B: USART2 Ready To Send */
-#define AT91_PA16_TPK0         (1 << 16)       /* A: Trace Packet Port 0 */
-#define AT91_PA16_CTS2         (1 << 16)       /* B: USART2 Clear To Send */
-#define AT91_PA17_TPK1         (1 << 17)       /* A: Trace Packet Port 1 */
-#define AT91_PA17_TF1          (1 << 17)       /* B: SSC1 Transmit Frame Sync 
*/
-#define AT91_PA18_TPK2         (1 << 18)       /* A: Trace Packet Port 2 */
-#define AT91_PA18_TK1          (1 << 18)       /* B: SSC1 Transmit Clock */
-#define AT91_PA19_TPK3         (1 << 19)       /* A: Trace Packet Port 3 */
-#define AT91_PA19_TD1          (1 << 19)       /* B: SSC1 Transmit Data */
-#define AT91_PA20_TPK4         (1 << 20)       /* A: Trace Packet Port 4 */
-#define AT91_PA20_RD1          (1 << 20)       /* B: SSC1 Receive Data */
-#define AT91_PA21_TPK5         (1 << 21)       /* A: Trace Packet Port 5 */
-#define AT91_PA21_RK1          (1 << 21)       /* B: SSC1 Receive Clock */
-#define AT91_PA22_TPK6         (1 << 22)       /* A: Trace Packet Port 6 */
-#define AT91_PA22_RF1          (1 << 22)       /* B: SSC1 Receive Frame Sync */
-#define AT91_PA23_TPK7         (1 << 23)       /* A: Trace Packet Port 7 */
-#define AT91_PA23_RTS0         (1 << 23)       /* B: USART0 Ready To Send */
-#define AT91_PA24_TPK8         (1 << 24)       /* A: Trace Packet Port 8 */
-#define AT91_PA24_SPI1_NPCS1   (1 << 24)       /* B: SPI1 Peripheral Chip 
Select 1 */
-#define AT91_PA25_TPK9         (1 << 25)       /* A: Trace Packet Port 9 */
-#define AT91_PA25_SPI1_NPCS2   (1 << 25)       /* B: SPI1 Peripheral Chip 
Select 2 */
-#define AT91_PA26_TPK10                (1 << 26)       /* A: Trace Packet Port 
10 */
-#define AT91_PA26_SPI1_NPCS3   (1 << 26)       /* B: SPI1 Peripheral Chip 
Select 3 */
-#define AT91_PA27_TPK11                (1 << 27)       /* A: Trace Packet Port 
11 */
-#define AT91_PA27_SPI0_NPCS1   (1 << 27)       /* B: SPI0 Peripheral Chip 
Select 1 */
-#define AT91_PA28_TPK12                (1 << 28)       /* A: Trace Packet Port 
12 */
-#define AT91_PA28_SPI0_NPCS2   (1 << 28)       /* B: SPI0 Peripheral Chip 
Select 2 */
-#define AT91_PA29_TPK13                (1 << 29)       /* A: Trace Packet Port 
13 */
-#define AT91_PA29_SPI0_NPCS3   (1 << 29)       /* B: SPI0 Peripheral Chip 
Select 3 */
-#define AT91_PA30_TPK14                (1 << 30)       /* A: Trace Packet Port 
14 */
-#define AT91_PA30_A23          (1 << 30)       /* B: Address Bus bit 23 */
-#define AT91_PA31_TPK15                (1 << 31)       /* A: Trace Packet Port 
15 */
-#define AT91_PA31_A24          (1 << 31)       /* B: Address Bus bit 24 */
-
-#define AT91_PB0_LCDVSYNC      (1 <<  0)       /* A: LCD Vertical 
Synchronization */
-#define AT91_PB1_LCDHSYNC      (1 <<  1)       /* A: LCD Horizontal 
Synchronization */
-#define AT91_PB2_LCDDOTCK      (1 <<  2)       /* A: LCD Dot Clock */
-#define AT91_PB2_PCK0          (1 <<  2)       /* B: PMC Programmable clock 
Output 0 */
-#define AT91_PB3_LCDDEN                (1 <<  3)       /* A: LCD Data Enable */
-#define AT91_PB4_LCDCC         (1 <<  4)       /* A: LCD Contrast Control */
-#define AT91_PB4_LCDD2         (1 <<  4)       /* B: LCD Data Bus Bit 2 */
-#define AT91_PB5_LCDD0         (1 <<  5)       /* A: LCD Data Bus Bit 0 */
-#define AT91_PB5_LCDD3         (1 <<  5)       /* B: LCD Data Bus Bit 3 */
-#define AT91_PB6_LCDD1         (1 <<  6)       /* A: LCD Data Bus Bit 1 */
-#define AT91_PB6_LCDD4         (1 <<  6)       /* B: LCD Data Bus Bit 4 */
-#define AT91_PB7_LCDD2         (1 <<  7)       /* A: LCD Data Bus Bit 2 */
-#define AT91_PB7_LCDD5         (1 <<  7)       /* B: LCD Data Bus Bit 5 */
-#define AT91_PB8_LCDD3         (1 <<  8)       /* A: LCD Data Bus Bit 3 */
-#define AT91_PB8_LCDD6         (1 <<  8)       /* B: LCD Data Bus Bit 6 */
-#define AT91_PB9_LCDD4         (1 <<  9)       /* A: LCD Data Bus Bit 4 */
-#define AT91_PB9_LCDD7         (1 <<  9)       /* B: LCD Data Bus Bit 7 */
-#define AT91_PB10_LCDD5                (1 << 10)       /* A: LCD Data Bus Bit 
5 */
-#define AT91_PB10_LCDD10       (1 << 10)       /* B: LCD Data Bus Bit 10 */
-#define AT91_PB11_LCDD6                (1 << 11)       /* A: LCD Data Bus Bit 
6 */
-#define AT91_PB11_LCDD11       (1 << 11)       /* B: LCD Data Bus Bit 11 */
-#define AT91_PB12_LCDD7                (1 << 12)       /* A: LCD Data Bus Bit 
7 */
-#define AT91_PB12_LCDD12       (1 << 12)       /* B: LCD Data Bus Bit 12 */
-#define AT91_PB13_LCDD8                (1 << 13)       /* A: LCD Data Bus Bit 
8 */
-#define AT91_PB13_LCDD13       (1 << 13)       /* B: LCD Data Bus Bit 13 */
-#define AT91_PB14_LCDD9                (1 << 14)       /* A: LCD Data Bus Bit 
9 */
-#define AT91_PB14_LCDD14       (1 << 14)       /* B: LCD Data Bus Bit 14 */
-#define AT91_PB15_LCDD10       (1 << 15)       /* A: LCD Data Bus Bit 10 */
-#define AT91_PB15_LCDD15       (1 << 15)       /* B: LCD Data Bus Bit 15 */
-#define AT91_PB16_LCDD11       (1 << 16)       /* A: LCD Data Bus Bit 11 */
-#define AT91_PB16_LCDD19       (1 << 16)       /* B: LCD Data Bus Bit 19 */
-#define AT91_PB17_LCDD12       (1 << 17)       /* A: LCD Data Bus Bit 12 */
-#define AT91_PB17_LCDD20       (1 << 17)       /* B: LCD Data Bus Bit 20 */
-#define AT91_PB18_LCDD13       (1 << 18)       /* A: LCD Data Bus Bit 13 */
-#define AT91_PB18_LCDD21       (1 << 18)       /* B: LCD Data Bus Bit 21 */
-#define AT91_PB19_LCDD14       (1 << 19)       /* A: LCD Data Bus Bit 14 */
-#define AT91_PB19_LCDD22       (1 << 19)       /* B: LCD Data Bus Bit 22 */
-#define AT91_PB20_LCDD15       (1 << 20)       /* A: LCD Data Bus Bit 15 */
-#define AT91_PB20_LCDD23       (1 << 20)       /* B: LCD Data Bus Bit 23 */
-#define AT91_PB21_TF0          (1 << 21)       /* A: SSC0 Transmit Frame Sync 
*/
-#define AT91_PB21_LCDD16       (1 << 21)       /* B: LCD Data Bus Bit 16 */
-#define AT91_PB22_TK0          (1 << 22)       /* A: SSC0 Transmit Clock */
-#define AT91_PB22_LCDD17       (1 << 22)       /* B: LCD Data Bus Bit 17 */
-#define AT91_PB23_TD0          (1 << 23)       /* A: SSC0 Transmit Data */
-#define AT91_PB23_LCDD18       (1 << 23)       /* B: LCD Data Bus Bit 18 */
-#define AT91_PB24_RD0          (1 << 24)       /* A: SSC0 Receive Data */
-#define AT91_PB24_LCDD19       (1 << 24)       /* B: LCD Data Bus Bit 19 */
-#define AT91_PB25_RK0          (1 << 25)       /* A: SSC0 Receive Clock */
-#define AT91_PB25_LCDD20       (1 << 25)       /* B: LCD Data Bus Bit 20 */
-#define AT91_PB26_RF0          (1 << 26)       /* A: SSC0 Receive Frame Sync */
-#define AT91_PB26_LCDD21       (1 << 26)       /* B: LCD Data Bus Bit 21 */
-#define AT91_PB27_SPI1_NPCS1   (1 << 27)       /* A: SPI1 Peripheral Chip 
Select 1 */
-#define AT91_PB27_LCDD22       (1 << 27)       /* B: LCD Data Bus Bit 22 */
-#define AT91_PB28_SPI1_NPCS0   (1 << 28)       /* A: SPI1 Peripheral Chip 
Select 0 */
-#define AT91_PB28_LCDD23       (1 << 28)       /* B: LCD Data Bus Bit 23 */
-#define AT91_PB29_SPI1_SPCK    (1 << 29)       /* A: SPI1 Serial Clock */
-#define AT91_PB29_IRQ2         (1 << 29)       /* B: Interrupt input 2 */
-#define AT91_PB30_SPI1_MISO    (1 << 30)       /* A: SPI1 Master In Slave */
-#define AT91_PB30_IRQ1         (1 << 30)       /* B: Interrupt input 1 */
-#define AT91_PB31_SPI1_MOSI    (1 << 31)       /* A: SPI1 Master Out Slave */
-#define AT91_PB31_PCK2         (1 << 31)       /* B: PMC Programmable clock 
Output 2 */
-
-#define AT91_PC0_SMOE          (1 << 0)        /* A: SmartMedia Output Enable 
*/
-#define AT91_PC0_NCS6          (1 << 0)        /* B: Chip Select 6 */
-#define AT91_PC1_SMWE          (1 << 1)        /* A: SmartMedia Write Enable */
-#define AT91_PC1_NCS7          (1 << 1)        /* B: Chip Select 7 */
-#define AT91_PC2_NWAIT         (1 << 2)        /* A: NWAIT */
-#define AT91_PC2_IRQ0          (1 << 2)        /* B: Interrupt input 0 */
-#define AT91_PC3_A25_CFRNW     (1 << 3)        /* A: Address Bus[25] / Compact 
Flash Read Not Write */
-#define AT91_PC4_NCS4_CFCS0    (1 << 4)        /* A: Chip Select 4 / 
CompactFlash Chip Select 0 */
-#define AT91_PC5_NCS5_CFCS1    (1 << 5)        /* A: Chip Select 5 / 
CompactFlash Chip Select 1 */
-#define AT91_PC6_CFCE1         (1 << 6)        /* A: CompactFlash Chip Enable 
1 */
-#define AT91_PC7_CFCE2         (1 << 7)        /* A: CompactFlash Chip Enable 
2 */
-#define AT91_PC8_TXD0          (1 << 8)        /* A: USART0 Transmit Data */
-#define AT91_PC8_PCK2          (1 << 8)        /* B: PMC Programmable clock 
Output 2 */
-#define AT91_PC9_RXD0          (1 << 9)        /* A: USART0 Receive Data */
-#define AT91_PC9_PCK3          (1 << 9)        /* B: PMC Programmable clock 
Output 3 */
-#define AT91_PC10_RTS0         (1 << 10)       /* A: USART0 Ready To Send */
-#define AT91_PC10_SCK0         (1 << 10)       /* B: USART0 Serial Clock */
-#define AT91_PC11_CTS0         (1 << 11)       /* A: USART0 Clear To Send */
-#define AT91_PC11_FIQ          (1 << 11)       /* B: AIC Fast Interrupt Input 
*/
-#define AT91_PC12_TXD1         (1 << 12)       /* A: USART1 Transmit Data */
-#define AT91_PC12_NCS6         (1 << 12)       /* B: Chip Select 6 */
-#define AT91_PC13_RXD1         (1 << 13)       /* A: USART1 Receive Data */
-#define AT91_PC13_NCS7         (1 << 13)       /* B: Chip Select 7 */
-#define AT91_PC14_TXD2         (1 << 14)       /* A: USART2 Transmit Data */
-#define AT91_PC14_SPI1_NPCS2   (1 << 14)       /* B: SPI1 Peripheral Chip 
Select 2 */
-#define AT91_PC15_RXD2         (1 << 15)       /* A: USART2 Receive Data */
-#define AT91_PC15_SPI1_NPCS3   (1 << 15)       /* B: SPI1 Peripheral Chip 
Select 3 */
-#define AT91_PC16_D16          (1 << 16)       /* A: Data Bus [16] */
-#define AT91_PC16_TCLK0                (1 << 16)       /* B: Timer Counter 0 
external clock input */
-#define AT91_PC17_D17          (1 << 17)       /* A: Data Bus [17] */
-#define AT91_PC17_TCLK1                (1 << 17)       /* B: Timer Counter 1 
external clock input */
-#define AT91_PC18_D18          (1 << 18)       /* A: Data Bus [18] */
-#define AT91_PC18_TCLK2                (1 << 18)       /* B: Timer Counter 2 
external clock input */
-#define AT91_PC19_D19          (1 << 19)       /* A: Data Bus [19] */
-#define AT91_PC19_TIOA0                (1 << 19)       /* B: Timer Counter 0 
Multipurpose Timer I/O Pin A */
-#define AT91_PC20_D20          (1 << 20)       /* A: Data Bus [20] */
-#define AT91_PC20_TIOB0                (1 << 20)       /* B: Timer Counter 0 
Multipurpose Timer I/O Pin B */
-#define AT91_PC21_D21          (1 << 21)       /* A: Data Bus [21] */
-#define AT91_PC21_TIOA1                (1 << 21)       /* B: Timer Counter 1 
Multipurpose Timer I/O Pin A */
-#define AT91_PC22_D22          (1 << 22)       /* A: Data Bus [22] */
-#define AT91_PC22_TIOB1                (1 << 22)       /* B: Timer Counter 1 
Multipurpose Timer I/O Pin B */
-#define AT91_PC23_D23          (1 << 23)       /* A: Data Bus [23] */
-#define AT91_PC23_TIOA2                (1 << 23)       /* B: Timer Counter 2 
Multipurpose Timer I/O Pin A */
-#define AT91_PC24_D24          (1 << 24)       /* A: Data Bus [24] */
-#define AT91_PC24_TIOB2                (1 << 24)       /* B: Timer Counter 2 
Multipurpose Timer I/O Pin B */
-#define AT91_PC25_D25          (1 << 25)       /* A: Data Bus [25] */
-#define AT91_PC25_TF2          (1 << 25)       /* B: SSC2 Transmit Frame Sync 
*/
-#define AT91_PC26_D26          (1 << 26)       /* A: Data Bus [26] */
-#define AT91_PC26_TK2          (1 << 26)       /* B: SSC2 Transmit Clock */
-#define AT91_PC27_D27          (1 << 27)       /* A: Data Bus [27] */
-#define AT91_PC27_TD2          (1 << 27)       /* B: SSC2 Transmit Data */
-#define AT91_PC28_D28          (1 << 28)       /* A: Data Bus [28] */
-#define AT91_PC28_RD2          (1 << 28)       /* B: SSC2 Receive Data */
-#define AT91_PC29_D29          (1 << 29)       /* A: Data Bus [29] */
-#define AT91_PC29_RK2          (1 << 29)       /* B: SSC2 Receive Clock */
-#define AT91_PC30_D30          (1 << 30)       /* A: Data Bus [30] */
-#define AT91_PC30_RF2          (1 << 30)       /* B: SSC2 Receive Frame Sync */
-#define AT91_PC31_D31          (1 << 31)       /* A: Data Bus [31] */
-#define AT91_PC31_PCK1         (1 << 31)       /* B: PMC Programmable clock 
Output 1 */
-#endif
-
 #endif
diff --git a/include/asm-arm/arch-at91/at91sam9263.h 
b/include/asm-arm/arch-at91/at91sam9263.h
index f4af68a..115c47a 100644
--- a/include/asm-arm/arch-at91/at91sam9263.h
+++ b/include/asm-arm/arch-at91/at91sam9263.h
@@ -119,13 +119,5 @@
 #define AT91SAM9263_DMAC_BASE  0x00800000      /* DMA Controller */
 #define AT91SAM9263_UHP_BASE   0x00a00000      /* USB Host controller */
 
-#if 0
-/*
- * PIO pin definitions (peripheral A/B multiplexing).
- */
-
-// TODO: Add
-
-#endif
 
 #endif
-
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