Gitweb:     
http://git.kernel.org/git/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commit;h=074f98df0547b7d15f78db9a17e985da0c22af28
Commit:     074f98df0547b7d15f78db9a17e985da0c22af28
Parent:     53f983a90d7908bcece51f86180c7c9b575a1e4d
Author:     Paul Mundt <[EMAIL PROTECTED]>
AuthorDate: Tue May 8 15:45:33 2007 +0900
Committer:  Paul Mundt <[EMAIL PROTECTED]>
CommitDate: Wed May 9 01:35:01 2007 +0000

    sh: Add 32-bit opcode feature CPU flag.
    
    Add a CPU flag for the CPUs that support 32-bit opcodes, which
    gets passed down to userspace.
    
    Signed-off-by: Paul Mundt <[EMAIL PROTECTED]>
---
 arch/sh/kernel/cpu/sh2a/probe.c |    1 +
 arch/sh/kernel/setup.c          |    2 +-
 include/asm-sh/cpu-features.h   |    1 +
 3 files changed, 3 insertions(+), 1 deletions(-)

diff --git a/arch/sh/kernel/cpu/sh2a/probe.c b/arch/sh/kernel/cpu/sh2a/probe.c
index 426f6db..f455c35 100644
--- a/arch/sh/kernel/cpu/sh2a/probe.c
+++ b/arch/sh/kernel/cpu/sh2a/probe.c
@@ -18,6 +18,7 @@ int __init detect_cpu_and_cache_system(void)
 {
        /* Just SH7206 for now .. */
        current_cpu_data.type                   = CPU_SH7206;
+       current_cpu_data.flags                  |= CPU_HAS_OP32;
 
        current_cpu_data.dcache.ways            = 4;
        current_cpu_data.dcache.way_incr        = (1 << 11);
diff --git a/arch/sh/kernel/setup.c b/arch/sh/kernel/setup.c
index 477d2a8..c277291 100644
--- a/arch/sh/kernel/setup.c
+++ b/arch/sh/kernel/setup.c
@@ -431,7 +431,7 @@ const char *get_cpu_subtype(struct sh_cpuinfo *c)
 /* Symbolic CPU flags, keep in sync with asm/cpu-features.h */
 static const char *cpu_flags[] = {
        "none", "fpu", "p2flush", "mmuassoc", "dsp", "perfctr",
-       "ptea", "llsc", "l2", NULL
+       "ptea", "llsc", "l2", "op32", NULL
 };
 
 static void show_cpuflags(struct seq_file *m, struct sh_cpuinfo *c)
diff --git a/include/asm-sh/cpu-features.h b/include/asm-sh/cpu-features.h
index 4bccd7c..86308aa 100644
--- a/include/asm-sh/cpu-features.h
+++ b/include/asm-sh/cpu-features.h
@@ -20,5 +20,6 @@
 #define CPU_HAS_PTEA           0x0020  /* PTEA register */
 #define CPU_HAS_LLSC           0x0040  /* movli.l/movco.l */
 #define CPU_HAS_L2_CACHE       0x0080  /* Secondary cache / URAM */
+#define CPU_HAS_OP32           0x0100  /* 32-bit instruction support */
 
 #endif /* __ASM_SH_CPU_FEATURES_H */
-
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