Gitweb:     
http://git.kernel.org/git/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commit;h=0d4f64681695b0e389f7121eb647b27c602990bc
Commit:     0d4f64681695b0e389f7121eb647b27c602990bc
Parent:     43c09ce7927912c7867617cba0a265beea38a154
Author:     Hirokazu Takata <[EMAIL PROTECTED]>
AuthorDate: Thu May 10 22:22:26 2007 -0700
Committer:  Linus Torvalds <[EMAIL PROTECTED]>
CommitDate: Fri May 11 08:29:33 2007 -0700

    m32r: fix tme_handler to check _PAGE_PRESENT bit
    
    Fix the tlb-miss handler (tme_handler) to check _PAGE_PRESENT bit
    in order to handle file-mapped or swapped-out pages correctly.
    
    This patch is required to fix unexpected page errors for m32r.
    
    Signed-off-by: Hitoshi Yamamoto <[EMAIL PROTECTED]>
    Signed-off-by: Hirokazu Takata <[EMAIL PROTECTED]>
    Signed-off-by: Andrew Morton <[EMAIL PROTECTED]>
    Signed-off-by: Linus Torvalds <[EMAIL PROTECTED]>
---
 arch/m32r/mm/mmu.S |   22 +++++++++++++---------
 1 files changed, 13 insertions(+), 9 deletions(-)

diff --git a/arch/m32r/mm/mmu.S b/arch/m32r/mm/mmu.S
index 8bb74b1..49a6d16 100644
--- a/arch/m32r/mm/mmu.S
+++ b/arch/m32r/mm/mmu.S
@@ -163,7 +163,8 @@ ENTRY(tme_handler)
 
        ; pte_data = (unsigned long)pte_val(*pte);
        ld      r2, @r3                 ; r2: pte data
-       or3     r2, r2, #2              ; _PAGE_PRESENT(=2)
+       and3    r3, r2, #2              ; _PAGE_PRESENT(=2) check
+       beqz    r3, 3f
 
        .fillinsn
 5:
@@ -264,11 +265,8 @@ ENTRY(tme_handler)
 ;
        and3    r1, r1, #0xeff
        ldi     r4, #611                ; _KERNPG_TABLE(=611)
-       beq     r1, r4, 4f              ; !pmd_bad(*pmd) ?
-       .fillinsn
-3:
-       ldi     r1, #0                  ; r1: pte_data = 0
-       bra     5f
+       bne     r1, r4, 3f              ; !pmd_bad(*pmd) ?
+
        .fillinsn
 4:
        ; pte = pte_offset(pmd, address);
@@ -282,8 +280,10 @@ ENTRY(tme_handler)
        add     r4, r3                  ; r4: pte
        ; pte_data = (unsigned long)pte_val(*pte);
        ld      r1, @r4                 ; r1: pte_data
-       .fillinsn
+       and3    r3, r1, #2              ; _PAGE_PRESENT(=2) check
+       beqz    r3, 3f
 
+       .fillinsn
 ;; set tlb
 ; r0: address, r1: pte_data, r2: entry
 ; r3,r4: (free)
@@ -295,8 +295,7 @@ ENTRY(tme_handler)
        and3    r4, r4, #(MMU_CONTEXT_ASID_MASK)
        or      r3, r4
        st      r3, @r2
-       or3     r4, r1, #2              ; _PAGE_PRESENT(=2)
-       st      r4, @(4,r2)             ; set_tlb_data(entry, pte_data);
+       st      r1, @(4,r2)             ; set_tlb_data(entry, pte_data);
 
        ld      r4, @sp+
        ld      r3, @sp+
@@ -306,6 +305,11 @@ ENTRY(tme_handler)
        ld      sp, @sp+
        rte
 
+       .fillinsn
+3:
+       ldi     r1, #2                  ; r1: pte_data = 0 | _PAGE_PRESENT(=2)
+       bra     5b
+
 #else
 #error unknown isa configuration
 #endif
-
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