Gitweb:     
http://git.kernel.org/git/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commit;h=877d7720f5f67793b9b6027840d2c88ea25dc4c8
Commit:     877d7720f5f67793b9b6027840d2c88ea25dc4c8
Parent:     9da7cf23a4f9690ceecfd0184cd050be564416f1
Author:     Andrew Victor <[EMAIL PROTECTED]>
AuthorDate: Fri May 11 20:49:56 2007 +0100
Committer:  Russell King <[EMAIL PROTECTED]>
CommitDate: Fri May 11 21:07:54 2007 +0100

    [ARM] 4370/3: AT91: Support for Atmel AT91SAM9RL processors.
    
    Add support for Atmel's new AT91SAM9RL range of processors.
    Includes similar peripherals as other AT91SAM9 processors, but with a
    High-speed USB controller and various sizes of internal SRAM.
    
    Signed-off-by: Nicolas Ferre <[EMAIL PROTECTED]>
    Signed-off-by: Andrew Victor <[EMAIL PROTECTED]>
    Signed-off-by: Russell King <[EMAIL PROTECTED]>
---
 arch/arm/mach-at91/Kconfig                    |    3 +
 arch/arm/mach-at91/Makefile                   |    1 +
 arch/arm/mach-at91/at91sam9rl.c               |  341 +++++++++++++
 arch/arm/mach-at91/at91sam9rl_devices.c       |  634 +++++++++++++++++++++++++
 arch/arm/mach-at91/generic.h                  |    2 +
 arch/arm/mm/Kconfig                           |    4 +-
 drivers/usb/gadget/Kconfig                    |    2 +-
 include/asm-arm/arch-at91/at91sam9rl.h        |  110 +++++
 include/asm-arm/arch-at91/at91sam9rl_matrix.h |   96 ++++
 include/asm-arm/arch-at91/cpu.h               |    9 +
 include/asm-arm/arch-at91/hardware.h          |    2 +
 include/asm-arm/arch-at91/timex.h             |    5 +
 include/asm-avr32/arch-at32ap/cpu.h           |    1 +
 13 files changed, 1207 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index 018d637..1ba120c 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -17,6 +17,9 @@ config ARCH_AT91SAM9261
 config ARCH_AT91SAM9263
        bool "AT91SAM9263"
 
+config ARCH_AT91SAM9RL
+       bool "AT91SAM9RL"
+
 endchoice
 
 # ----------------------------------------------------------
diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index a412ae1..66d79e6 100644
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -14,6 +14,7 @@ obj-$(CONFIG_ARCH_AT91RM9200) += at91rm9200.o 
at91rm9200_time.o at91rm9200_devic
 obj-$(CONFIG_ARCH_AT91SAM9260) += at91sam9260.o at91sam926x_time.o 
at91sam9260_devices.o
 obj-$(CONFIG_ARCH_AT91SAM9261) += at91sam9261.o at91sam926x_time.o 
at91sam9261_devices.o
 obj-$(CONFIG_ARCH_AT91SAM9263) += at91sam9263.o at91sam926x_time.o 
at91sam9263_devices.o
+obj-$(CONFIG_ARCH_AT91SAM9RL)  += at91sam9rl.o at91sam926x_time.o 
at91sam9rl_devices.o
 
 # AT91RM9200 board-specific support
 obj-$(CONFIG_MACH_ONEARM)      += board-1arm.o
diff --git a/arch/arm/mach-at91/at91sam9rl.c b/arch/arm/mach-at91/at91sam9rl.c
new file mode 100644
index 0000000..4813a35
--- /dev/null
+++ b/arch/arm/mach-at91/at91sam9rl.c
@@ -0,0 +1,341 @@
+/*
+ * arch/arm/mach-at91/at91sam9rl.c
+ *
+ *  Copyright (C) 2005 SAN People
+ *  Copyright (C) 2007 Atmel Corporation
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file COPYING in the main directory of this archive for
+ * more details.
+ */
+
+#include <linux/module.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/at91sam9rl.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/at91_rstc.h>
+
+#include "generic.h"
+#include "clock.h"
+
+static struct map_desc at91sam9rl_io_desc[] __initdata = {
+       {
+               .virtual        = AT91_VA_BASE_SYS,
+               .pfn            = __phys_to_pfn(AT91_BASE_SYS),
+               .length         = SZ_16K,
+               .type           = MT_DEVICE,
+       },
+};
+
+static struct map_desc at91sam9rl_sram_desc[] __initdata = {
+       {
+               .pfn            = __phys_to_pfn(AT91SAM9RL_SRAM_BASE),
+               .type           = MT_DEVICE,
+       }
+};
+
+/* --------------------------------------------------------------------
+ *  Clocks
+ * -------------------------------------------------------------------- */
+
+/*
+ * The peripheral clocks.
+ */
+static struct clk pioA_clk = {
+       .name           = "pioA_clk",
+       .pmc_mask       = 1 << AT91SAM9RL_ID_PIOA,
+       .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk pioB_clk = {
+       .name           = "pioB_clk",
+       .pmc_mask       = 1 << AT91SAM9RL_ID_PIOB,
+       .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk pioC_clk = {
+       .name           = "pioC_clk",
+       .pmc_mask       = 1 << AT91SAM9RL_ID_PIOC,
+       .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk pioD_clk = {
+       .name           = "pioD_clk",
+       .pmc_mask       = 1 << AT91SAM9RL_ID_PIOD,
+       .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk usart0_clk = {
+       .name           = "usart0_clk",
+       .pmc_mask       = 1 << AT91SAM9RL_ID_US0,
+       .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk usart1_clk = {
+       .name           = "usart1_clk",
+       .pmc_mask       = 1 << AT91SAM9RL_ID_US1,
+       .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk usart2_clk = {
+       .name           = "usart2_clk",
+       .pmc_mask       = 1 << AT91SAM9RL_ID_US2,
+       .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk usart3_clk = {
+       .name           = "usart3_clk",
+       .pmc_mask       = 1 << AT91SAM9RL_ID_US3,
+       .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk mmc_clk = {
+       .name           = "mci_clk",
+       .pmc_mask       = 1 << AT91SAM9RL_ID_MCI,
+       .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk twi0_clk = {
+       .name           = "twi0_clk",
+       .pmc_mask       = 1 << AT91SAM9RL_ID_TWI0,
+       .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk twi1_clk = {
+       .name           = "twi1_clk",
+       .pmc_mask       = 1 << AT91SAM9RL_ID_TWI1,
+       .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk spi_clk = {
+       .name           = "spi_clk",
+       .pmc_mask       = 1 << AT91SAM9RL_ID_SPI,
+       .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk ssc0_clk = {
+       .name           = "ssc0_clk",
+       .pmc_mask       = 1 << AT91SAM9RL_ID_SSC0,
+       .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk ssc1_clk = {
+       .name           = "ssc1_clk",
+       .pmc_mask       = 1 << AT91SAM9RL_ID_SSC1,
+       .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk tc0_clk = {
+       .name           = "tc0_clk",
+       .pmc_mask       = 1 << AT91SAM9RL_ID_TC0,
+       .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk tc1_clk = {
+       .name           = "tc1_clk",
+       .pmc_mask       = 1 << AT91SAM9RL_ID_TC1,
+       .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk tc2_clk = {
+       .name           = "tc2_clk",
+       .pmc_mask       = 1 << AT91SAM9RL_ID_TC2,
+       .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk pwmc_clk = {
+       .name           = "pwmc_clk",
+       .pmc_mask       = 1 << AT91SAM9RL_ID_PWMC,
+       .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk tsc_clk = {
+       .name           = "tsc_clk",
+       .pmc_mask       = 1 << AT91SAM9RL_ID_TSC,
+       .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk dma_clk = {
+       .name           = "dma_clk",
+       .pmc_mask       = 1 << AT91SAM9RL_ID_DMA,
+       .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk udphs_clk = {
+       .name           = "udphs_clk",
+       .pmc_mask       = 1 << AT91SAM9RL_ID_UDPHS,
+       .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk lcdc_clk = {
+       .name           = "lcdc_clk",
+       .pmc_mask       = 1 << AT91SAM9RL_ID_LCDC,
+       .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk ac97_clk = {
+       .name           = "ac97_clk",
+       .pmc_mask       = 1 << AT91SAM9RL_ID_AC97C,
+       .type           = CLK_TYPE_PERIPHERAL,
+};
+
+static struct clk *periph_clocks[] __initdata = {
+       &pioA_clk,
+       &pioB_clk,
+       &pioC_clk,
+       &pioD_clk,
+       &usart0_clk,
+       &usart1_clk,
+       &usart2_clk,
+       &usart3_clk,
+       &mmc_clk,
+       &twi0_clk,
+       &twi1_clk,
+       &spi_clk,
+       &ssc0_clk,
+       &ssc1_clk,
+       &tc0_clk,
+       &tc1_clk,
+       &tc2_clk,
+       &pwmc_clk,
+       &tsc_clk,
+       &dma_clk,
+       &udphs_clk,
+       &lcdc_clk,
+       &ac97_clk,
+       // irq0
+};
+
+/*
+ * The two programmable clocks.
+ * You must configure pin multiplexing to bring these signals out.
+ */
+static struct clk pck0 = {
+       .name           = "pck0",
+       .pmc_mask       = AT91_PMC_PCK0,
+       .type           = CLK_TYPE_PROGRAMMABLE,
+       .id             = 0,
+};
+static struct clk pck1 = {
+       .name           = "pck1",
+       .pmc_mask       = AT91_PMC_PCK1,
+       .type           = CLK_TYPE_PROGRAMMABLE,
+       .id             = 1,
+};
+
+static void __init at91sam9rl_register_clocks(void)
+{
+       int i;
+
+       for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
+               clk_register(periph_clocks[i]);
+
+       clk_register(&pck0);
+       clk_register(&pck1);
+}
+
+/* --------------------------------------------------------------------
+ *  GPIO
+ * -------------------------------------------------------------------- */
+
+static struct at91_gpio_bank at91sam9rl_gpio[] = {
+       {
+               .id             = AT91SAM9RL_ID_PIOA,
+               .offset         = AT91_PIOA,
+               .clock          = &pioA_clk,
+       }, {
+               .id             = AT91SAM9RL_ID_PIOB,
+               .offset         = AT91_PIOB,
+               .clock          = &pioB_clk,
+       }, {
+               .id             = AT91SAM9RL_ID_PIOC,
+               .offset         = AT91_PIOC,
+               .clock          = &pioC_clk,
+       }, {
+               .id             = AT91SAM9RL_ID_PIOD,
+               .offset         = AT91_PIOD,
+               .clock          = &pioD_clk,
+       }
+};
+
+static void at91sam9rl_reset(void)
+{
+       at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | 
AT91_RSTC_PERRST);
+}
+
+
+/* --------------------------------------------------------------------
+ *  AT91SAM9RL processor initialization
+ * -------------------------------------------------------------------- */
+
+void __init at91sam9rl_initialize(unsigned long main_clock)
+{
+       unsigned long cidr, sram_size;
+
+       /* Map peripherals */
+       iotable_init(at91sam9rl_io_desc, ARRAY_SIZE(at91sam9rl_io_desc));
+
+       cidr = at91_sys_read(AT91_DBGU_CIDR);
+
+       switch (cidr & AT91_CIDR_SRAMSIZ) {
+               case AT91_CIDR_SRAMSIZ_32K:
+                       sram_size = 2 * SZ_16K;
+                       break;
+               case AT91_CIDR_SRAMSIZ_16K:
+               default:
+                       sram_size = SZ_16K;
+       }
+
+       at91sam9rl_sram_desc->virtual = AT91_IO_VIRT_BASE - sram_size;
+       at91sam9rl_sram_desc->length = sram_size;
+
+       /* Map SRAM */
+       iotable_init(at91sam9rl_sram_desc, ARRAY_SIZE(at91sam9rl_sram_desc));
+
+       at91_arch_reset = at91sam9rl_reset;
+       at91_extern_irq = (1 << AT91SAM9RL_ID_IRQ0);
+
+       /* Init clock subsystem */
+       at91_clock_init(main_clock);
+
+       /* Register the processor-specific clocks */
+       at91sam9rl_register_clocks();
+
+       /* Register GPIO subsystem */
+       at91_gpio_init(at91sam9rl_gpio, 4);
+}
+
+/* --------------------------------------------------------------------
+ *  Interrupt initialization
+ * -------------------------------------------------------------------- */
+
+/*
+ * The default interrupt priority levels (0 = lowest, 7 = highest).
+ */
+static unsigned int at91sam9rl_default_irq_priority[NR_AIC_IRQS] __initdata = {
+       7,      /* Advanced Interrupt Controller */
+       7,      /* System Peripherals */
+       1,      /* Parallel IO Controller A */
+       1,      /* Parallel IO Controller B */
+       1,      /* Parallel IO Controller C */
+       1,      /* Parallel IO Controller D */
+       5,      /* USART 0 */
+       5,      /* USART 1 */
+       5,      /* USART 2 */
+       5,      /* USART 3 */
+       0,      /* Multimedia Card Interface */
+       6,      /* Two-Wire Interface 0 */
+       6,      /* Two-Wire Interface 1 */
+       5,      /* Serial Peripheral Interface */
+       4,      /* Serial Synchronous Controller 0 */
+       4,      /* Serial Synchronous Controller 1 */
+       0,      /* Timer Counter 0 */
+       0,      /* Timer Counter 1 */
+       0,      /* Timer Counter 2 */
+       0,
+       0,      /* Touch Screen Controller */
+       0,      /* DMA Controller */
+       2,      /* USB Device High speed port */
+       2,      /* LCD Controller */
+       6,      /* AC97 Controller */
+       0,
+       0,
+       0,
+       0,
+       0,
+       0,
+       0,      /* Advanced Interrupt Controller */
+};
+
+void __init at91sam9rl_init_interrupts(unsigned int priority[NR_AIC_IRQS])
+{
+       if (!priority)
+               priority = at91sam9rl_default_irq_priority;
+
+       /* Initialize the AIC interrupt controller */
+       at91_aic_init(priority);
+
+       /* Enable GPIO interrupts */
+       at91_gpio_irq_setup();
+}
diff --git a/arch/arm/mach-at91/at91sam9rl_devices.c 
b/arch/arm/mach-at91/at91sam9rl_devices.c
new file mode 100644
index 0000000..e775aa6
--- /dev/null
+++ b/arch/arm/mach-at91/at91sam9rl_devices.c
@@ -0,0 +1,634 @@
+/*
+ *  Copyright (C) 2007 Atmel Corporation
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file COPYING in the main directory of this archive for
+ * more details.
+ */
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+
+#include <linux/platform_device.h>
+#include <linux/fb.h>
+
+#include <video/atmel_lcdc.h>
+
+#include <asm/arch/board.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/at91sam9rl.h>
+#include <asm/arch/at91sam9rl_matrix.h>
+#include <asm/arch/at91sam926x_mc.h>
+
+#include "generic.h"
+
+#define SZ_512 0x00000200
+#define SZ_256 0x00000100
+#define SZ_16  0x00000010
+
+
+/* --------------------------------------------------------------------
+ *  MMC / SD
+ * -------------------------------------------------------------------- */
+
+#if defined(CONFIG_MMC_AT91) || defined(CONFIG_MMC_AT91_MODULE)
+static u64 mmc_dmamask = 0xffffffffUL;
+static struct at91_mmc_data mmc_data;
+
+static struct resource mmc_resources[] = {
+       [0] = {
+               .start  = AT91SAM9RL_BASE_MCI,
+               .end    = AT91SAM9RL_BASE_MCI + SZ_16K - 1,
+               .flags  = IORESOURCE_MEM,
+       },
+       [1] = {
+               .start  = AT91SAM9RL_ID_MCI,
+               .end    = AT91SAM9RL_ID_MCI,
+               .flags  = IORESOURCE_IRQ,
+       },
+};
+
+static struct platform_device at91sam9rl_mmc_device = {
+       .name           = "at91_mci",
+       .id             = -1,
+       .dev            = {
+                               .dma_mask               = &mmc_dmamask,
+                               .coherent_dma_mask      = 0xffffffff,
+                               .platform_data          = &mmc_data,
+       },
+       .resource       = mmc_resources,
+       .num_resources  = ARRAY_SIZE(mmc_resources),
+};
+
+void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data)
+{
+       if (!data)
+               return;
+
+       /* input/irq */
+       if (data->det_pin) {
+               at91_set_gpio_input(data->det_pin, 1);
+               at91_set_deglitch(data->det_pin, 1);
+       }
+       if (data->wp_pin)
+               at91_set_gpio_input(data->wp_pin, 1);
+       if (data->vcc_pin)
+               at91_set_gpio_output(data->vcc_pin, 0);
+
+       /* CLK */
+       at91_set_A_periph(AT91_PIN_PA2, 0);
+
+       /* CMD */
+       at91_set_A_periph(AT91_PIN_PA1, 1);
+
+       /* DAT0, maybe DAT1..DAT3 */
+       at91_set_A_periph(AT91_PIN_PA0, 1);
+       if (data->wire4) {
+               at91_set_A_periph(AT91_PIN_PA3, 1);
+               at91_set_A_periph(AT91_PIN_PA4, 1);
+               at91_set_A_periph(AT91_PIN_PA5, 1);
+       }
+
+       mmc_data = *data;
+       platform_device_register(&at91sam9rl_mmc_device);
+}
+#else
+void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data) {}
+#endif
+
+
+/* --------------------------------------------------------------------
+ *  NAND / SmartMedia
+ * -------------------------------------------------------------------- */
+
+#if defined(CONFIG_MTD_NAND_AT91) || defined(CONFIG_MTD_NAND_AT91_MODULE)
+static struct at91_nand_data nand_data;
+
+#define NAND_BASE      AT91_CHIPSELECT_3
+
+static struct resource nand_resources[] = {
+       {
+               .start  = NAND_BASE,
+               .end    = NAND_BASE + SZ_256M - 1,
+               .flags  = IORESOURCE_MEM,
+       }
+};
+
+static struct platform_device at91_nand_device = {
+       .name           = "at91_nand",
+       .id             = -1,
+       .dev            = {
+                               .platform_data  = &nand_data,
+       },
+       .resource       = nand_resources,
+       .num_resources  = ARRAY_SIZE(nand_resources),
+};
+
+void __init at91_add_device_nand(struct at91_nand_data *data)
+{
+       unsigned long csa;
+
+       if (!data)
+               return;
+
+       csa = at91_sys_read(AT91_MATRIX_EBICSA);
+       at91_sys_write(AT91_MATRIX_EBICSA, csa | 
AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
+
+       /* set the bus interface characteristics */
+       at91_sys_write(AT91_SMC_SETUP(3), AT91_SMC_NWESETUP_(0) | 
AT91_SMC_NCS_WRSETUP_(0)
+                       | AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0));
+
+       at91_sys_write(AT91_SMC_PULSE(3), AT91_SMC_NWEPULSE_(2) | 
AT91_SMC_NCS_WRPULSE_(5)
+                       | AT91_SMC_NRDPULSE_(2) | AT91_SMC_NCS_RDPULSE_(5));
+
+       at91_sys_write(AT91_SMC_CYCLE(3), AT91_SMC_NWECYCLE_(7) | 
AT91_SMC_NRDCYCLE_(7));
+
+       at91_sys_write(AT91_SMC_MODE(3), AT91_SMC_DBW_8 | AT91_SMC_READMODE | 
AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_TDF_(1));
+
+       /* enable pin */
+       if (data->enable_pin)
+               at91_set_gpio_output(data->enable_pin, 1);
+
+       /* ready/busy pin */
+       if (data->rdy_pin)
+               at91_set_gpio_input(data->rdy_pin, 1);
+
+       /* card detect pin */
+       if (data->det_pin)
+               at91_set_gpio_input(data->det_pin, 1);
+
+       at91_set_A_periph(AT91_PIN_PB4, 0);             /* NANDOE */
+       at91_set_A_periph(AT91_PIN_PB5, 0);             /* NANDWE */
+
+       nand_data = *data;
+       platform_device_register(&at91_nand_device);
+}
+
+#else
+void __init at91_add_device_nand(struct at91_nand_data *data) {}
+#endif
+
+
+/* --------------------------------------------------------------------
+ *  TWI (i2c)
+ * -------------------------------------------------------------------- */
+
+#if defined(CONFIG_I2C_AT91) || defined(CONFIG_I2C_AT91_MODULE)
+
+static struct resource twi_resources[] = {
+       [0] = {
+               .start  = AT91SAM9RL_BASE_TWI0,
+               .end    = AT91SAM9RL_BASE_TWI0 + SZ_16K - 1,
+               .flags  = IORESOURCE_MEM,
+       },
+       [1] = {
+               .start  = AT91SAM9RL_ID_TWI0,
+               .end    = AT91SAM9RL_ID_TWI0,
+               .flags  = IORESOURCE_IRQ,
+       },
+};
+
+static struct platform_device at91sam9rl_twi_device = {
+       .name           = "at91_i2c",
+       .id             = -1,
+       .resource       = twi_resources,
+       .num_resources  = ARRAY_SIZE(twi_resources),
+};
+
+void __init at91_add_device_i2c(void)
+{
+       /* pins used for TWI interface */
+       at91_set_A_periph(AT91_PIN_PA23, 0);            /* TWD */
+       at91_set_multi_drive(AT91_PIN_PA23, 1);
+
+       at91_set_A_periph(AT91_PIN_PA24, 0);            /* TWCK */
+       at91_set_multi_drive(AT91_PIN_PA24, 1);
+
+       platform_device_register(&at91sam9rl_twi_device);
+}
+#else
+void __init at91_add_device_i2c(void) {}
+#endif
+
+
+/* --------------------------------------------------------------------
+ *  SPI
+ * -------------------------------------------------------------------- */
+
+#if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE)
+static u64 spi_dmamask = 0xffffffffUL;
+
+static struct resource spi_resources[] = {
+       [0] = {
+               .start  = AT91SAM9RL_BASE_SPI,
+               .end    = AT91SAM9RL_BASE_SPI + SZ_16K - 1,
+               .flags  = IORESOURCE_MEM,
+       },
+       [1] = {
+               .start  = AT91SAM9RL_ID_SPI,
+               .end    = AT91SAM9RL_ID_SPI,
+               .flags  = IORESOURCE_IRQ,
+       },
+};
+
+static struct platform_device at91sam9rl_spi_device = {
+       .name           = "atmel_spi",
+       .id             = 0,
+       .dev            = {
+                               .dma_mask               = &spi_dmamask,
+                               .coherent_dma_mask      = 0xffffffff,
+       },
+       .resource       = spi_resources,
+       .num_resources  = ARRAY_SIZE(spi_resources),
+};
+
+static const unsigned spi_standard_cs[4] = { AT91_PIN_PA28, AT91_PIN_PB7, 
AT91_PIN_PD8, AT91_PIN_PD9 };
+
+
+void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
+{
+       int i;
+       unsigned long cs_pin;
+
+       at91_set_A_periph(AT91_PIN_PA25, 0);    /* MISO */
+       at91_set_A_periph(AT91_PIN_PA26, 0);    /* MOSI */
+       at91_set_A_periph(AT91_PIN_PA27, 0);    /* SPCK */
+
+       /* Enable SPI chip-selects */
+       for (i = 0; i < nr_devices; i++) {
+               if (devices[i].controller_data)
+                       cs_pin = (unsigned long) devices[i].controller_data;
+               else
+                       cs_pin = spi_standard_cs[devices[i].chip_select];
+
+               /* enable chip-select pin */
+               at91_set_gpio_output(cs_pin, 1);
+
+               /* pass chip-select pin to driver */
+               devices[i].controller_data = (void *) cs_pin;
+       }
+
+       spi_register_board_info(devices, nr_devices);
+       platform_device_register(&at91sam9rl_spi_device);
+}
+#else
+void __init at91_add_device_spi(struct spi_board_info *devices, int 
nr_devices) {}
+#endif
+
+
+/* --------------------------------------------------------------------
+ *  LCD Controller
+ * -------------------------------------------------------------------- */
+
+#if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE)
+static u64 lcdc_dmamask = 0xffffffffUL;
+static struct atmel_lcdfb_info lcdc_data;
+
+static struct resource lcdc_resources[] = {
+       [0] = {
+               .start  = AT91SAM9RL_LCDC_BASE,
+               .end    = AT91SAM9RL_LCDC_BASE + SZ_4K - 1,
+               .flags  = IORESOURCE_MEM,
+       },
+       [1] = {
+               .start  = AT91SAM9RL_ID_LCDC,
+               .end    = AT91SAM9RL_ID_LCDC,
+               .flags  = IORESOURCE_IRQ,
+       },
+#if defined(CONFIG_FB_INTSRAM)
+       [2] = {
+               .start  = AT91SAM9RL_SRAM_BASE,
+               .end    = AT91SAM9RL_SRAM_BASE + AT91SAM9RL_SRAM_SIZE - 1,
+               .flags  = IORESOURCE_MEM,
+       },
+#endif
+};
+
+static struct platform_device at91_lcdc_device = {
+       .name           = "atmel_lcdfb",
+       .id             = 0,
+       .dev            = {
+                               .dma_mask               = &lcdc_dmamask,
+                               .coherent_dma_mask      = 0xffffffff,
+                               .platform_data          = &lcdc_data,
+       },
+       .resource       = lcdc_resources,
+       .num_resources  = ARRAY_SIZE(lcdc_resources),
+};
+
+void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data)
+{
+       if (!data) {
+               return;
+       }
+
+       at91_set_B_periph(AT91_PIN_PC1, 0);     /* LCDPWR */
+       at91_set_A_periph(AT91_PIN_PC5, 0);     /* LCDHSYNC */
+       at91_set_A_periph(AT91_PIN_PC6, 0);     /* LCDDOTCK */
+       at91_set_A_periph(AT91_PIN_PC7, 0);     /* LCDDEN */
+       at91_set_A_periph(AT91_PIN_PC3, 0);     /* LCDCC */
+       at91_set_B_periph(AT91_PIN_PC9, 0);     /* LCDD3 */
+       at91_set_B_periph(AT91_PIN_PC10, 0);    /* LCDD4 */
+       at91_set_B_periph(AT91_PIN_PC11, 0);    /* LCDD5 */
+       at91_set_B_periph(AT91_PIN_PC12, 0);    /* LCDD6 */
+       at91_set_B_periph(AT91_PIN_PC13, 0);    /* LCDD7 */
+       at91_set_B_periph(AT91_PIN_PC15, 0);    /* LCDD11 */
+       at91_set_B_periph(AT91_PIN_PC16, 0);    /* LCDD12 */
+       at91_set_B_periph(AT91_PIN_PC17, 0);    /* LCDD13 */
+       at91_set_B_periph(AT91_PIN_PC18, 0);    /* LCDD14 */
+       at91_set_B_periph(AT91_PIN_PC19, 0);    /* LCDD15 */
+       at91_set_B_periph(AT91_PIN_PC20, 0);    /* LCDD18 */
+       at91_set_B_periph(AT91_PIN_PC21, 0);    /* LCDD19 */
+       at91_set_B_periph(AT91_PIN_PC22, 0);    /* LCDD20 */
+       at91_set_B_periph(AT91_PIN_PC23, 0);    /* LCDD21 */
+       at91_set_B_periph(AT91_PIN_PC24, 0);    /* LCDD22 */
+       at91_set_B_periph(AT91_PIN_PC25, 0);    /* LCDD23 */
+
+       lcdc_data = *data;
+       platform_device_register(&at91_lcdc_device);
+}
+#else
+void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data) {}
+#endif
+
+
+/* --------------------------------------------------------------------
+ *  LEDs
+ * -------------------------------------------------------------------- */
+
+#if defined(CONFIG_LEDS)
+u8 at91_leds_cpu;
+u8 at91_leds_timer;
+
+void __init at91_init_leds(u8 cpu_led, u8 timer_led)
+{
+       /* Enable GPIO to access the LEDs */
+       at91_set_gpio_output(cpu_led, 1);
+       at91_set_gpio_output(timer_led, 1);
+
+       at91_leds_cpu   = cpu_led;
+       at91_leds_timer = timer_led;
+}
+#else
+void __init at91_init_leds(u8 cpu_led, u8 timer_led) {}
+#endif
+
+
+/* --------------------------------------------------------------------
+ *  UART
+ * -------------------------------------------------------------------- */
+
+#if defined(CONFIG_SERIAL_ATMEL)
+static struct resource dbgu_resources[] = {
+       [0] = {
+               .start  = AT91_VA_BASE_SYS + AT91_DBGU,
+               .end    = AT91_VA_BASE_SYS + AT91_DBGU + SZ_512 - 1,
+               .flags  = IORESOURCE_MEM,
+       },
+       [1] = {
+               .start  = AT91_ID_SYS,
+               .end    = AT91_ID_SYS,
+               .flags  = IORESOURCE_IRQ,
+       },
+};
+
+static struct atmel_uart_data dbgu_data = {
+       .use_dma_tx     = 0,
+       .use_dma_rx     = 0,            /* DBGU not capable of receive DMA */
+       .regs           = (void __iomem *)(AT91_VA_BASE_SYS + AT91_DBGU),
+};
+
+static struct platform_device at91sam9rl_dbgu_device = {
+       .name           = "atmel_usart",
+       .id             = 0,
+       .dev            = {
+                               .platform_data  = &dbgu_data,
+                               .coherent_dma_mask = 0xffffffff,
+       },
+       .resource       = dbgu_resources,
+       .num_resources  = ARRAY_SIZE(dbgu_resources),
+};
+
+static inline void configure_dbgu_pins(void)
+{
+       at91_set_A_periph(AT91_PIN_PA21, 0);            /* DRXD */
+       at91_set_A_periph(AT91_PIN_PA22, 1);            /* DTXD */
+}
+
+static struct resource uart0_resources[] = {
+       [0] = {
+               .start  = AT91SAM9RL_BASE_US0,
+               .end    = AT91SAM9RL_BASE_US0 + SZ_16K - 1,
+               .flags  = IORESOURCE_MEM,
+       },
+       [1] = {
+               .start  = AT91SAM9RL_ID_US0,
+               .end    = AT91SAM9RL_ID_US0,
+               .flags  = IORESOURCE_IRQ,
+       },
+};
+
+static struct atmel_uart_data uart0_data = {
+       .use_dma_tx     = 1,
+       .use_dma_rx     = 1,
+};
+
+static struct platform_device at91sam9rl_uart0_device = {
+       .name           = "atmel_usart",
+       .id             = 1,
+       .dev            = {
+                               .platform_data  = &uart0_data,
+                               .coherent_dma_mask = 0xffffffff,
+       },
+       .resource       = uart0_resources,
+       .num_resources  = ARRAY_SIZE(uart0_resources),
+};
+
+static inline void configure_usart0_pins(void)
+{
+       at91_set_A_periph(AT91_PIN_PA6, 1);             /* TXD0 */
+       at91_set_A_periph(AT91_PIN_PA7, 0);             /* RXD0 */
+       at91_set_A_periph(AT91_PIN_PA9, 0);             /* RTS0 */
+       at91_set_A_periph(AT91_PIN_PA10, 0);            /* CTS0 */
+}
+
+static struct resource uart1_resources[] = {
+       [0] = {
+               .start  = AT91SAM9RL_BASE_US1,
+               .end    = AT91SAM9RL_BASE_US1 + SZ_16K - 1,
+               .flags  = IORESOURCE_MEM,
+       },
+       [1] = {
+               .start  = AT91SAM9RL_ID_US1,
+               .end    = AT91SAM9RL_ID_US1,
+               .flags  = IORESOURCE_IRQ,
+       },
+};
+
+static struct atmel_uart_data uart1_data = {
+       .use_dma_tx     = 1,
+       .use_dma_rx     = 1,
+};
+
+static struct platform_device at91sam9rl_uart1_device = {
+       .name           = "atmel_usart",
+       .id             = 2,
+       .dev            = {
+                               .platform_data  = &uart1_data,
+                               .coherent_dma_mask = 0xffffffff,
+       },
+       .resource       = uart1_resources,
+       .num_resources  = ARRAY_SIZE(uart1_resources),
+};
+
+static inline void configure_usart1_pins(void)
+{
+       at91_set_A_periph(AT91_PIN_PA11, 1);            /* TXD1 */
+       at91_set_A_periph(AT91_PIN_PA12, 0);            /* RXD1 */
+}
+
+static struct resource uart2_resources[] = {
+       [0] = {
+               .start  = AT91SAM9RL_BASE_US2,
+               .end    = AT91SAM9RL_BASE_US2 + SZ_16K - 1,
+               .flags  = IORESOURCE_MEM,
+       },
+       [1] = {
+               .start  = AT91SAM9RL_ID_US2,
+               .end    = AT91SAM9RL_ID_US2,
+               .flags  = IORESOURCE_IRQ,
+       },
+};
+
+static struct atmel_uart_data uart2_data = {
+       .use_dma_tx     = 1,
+       .use_dma_rx     = 1,
+};
+
+static struct platform_device at91sam9rl_uart2_device = {
+       .name           = "atmel_usart",
+       .id             = 3,
+       .dev            = {
+                               .platform_data  = &uart2_data,
+                               .coherent_dma_mask = 0xffffffff,
+       },
+       .resource       = uart2_resources,
+       .num_resources  = ARRAY_SIZE(uart2_resources),
+};
+
+static inline void configure_usart2_pins(void)
+{
+       at91_set_A_periph(AT91_PIN_PA13, 1);            /* TXD2 */
+       at91_set_A_periph(AT91_PIN_PA14, 0);            /* RXD2 */
+}
+
+static struct resource uart3_resources[] = {
+       [0] = {
+               .start  = AT91SAM9RL_BASE_US3,
+               .end    = AT91SAM9RL_BASE_US3 + SZ_16K - 1,
+               .flags  = IORESOURCE_MEM,
+       },
+       [1] = {
+               .start  = AT91SAM9RL_ID_US3,
+               .end    = AT91SAM9RL_ID_US3,
+               .flags  = IORESOURCE_IRQ,
+       },
+};
+
+static struct atmel_uart_data uart3_data = {
+       .use_dma_tx     = 1,
+       .use_dma_rx     = 1,
+};
+
+static struct platform_device at91sam9rl_uart3_device = {
+       .name           = "atmel_usart",
+       .id             = 4,
+       .dev            = {
+                               .platform_data  = &uart3_data,
+                               .coherent_dma_mask = 0xffffffff,
+       },
+       .resource       = uart3_resources,
+       .num_resources  = ARRAY_SIZE(uart3_resources),
+};
+
+static inline void configure_usart3_pins(void)
+{
+       at91_set_A_periph(AT91_PIN_PB0, 1);             /* TXD3 */
+       at91_set_A_periph(AT91_PIN_PB1, 0);             /* RXD3 */
+}
+
+struct platform_device *at91_uarts[ATMEL_MAX_UART];    /* the UARTs to use */
+struct platform_device *atmel_default_console_device;  /* the serial console 
device */
+
+void __init at91_init_serial(struct at91_uart_config *config)
+{
+       int i;
+
+       /* Fill in list of supported UARTs */
+       for (i = 0; i < config->nr_tty; i++) {
+               switch (config->tty_map[i]) {
+                       case 0:
+                               configure_usart0_pins();
+                               at91_uarts[i] = &at91sam9rl_uart0_device;
+                               at91_clock_associate("usart0_clk", 
&at91sam9rl_uart0_device.dev, "usart");
+                               break;
+                       case 1:
+                               configure_usart1_pins();
+                               at91_uarts[i] = &at91sam9rl_uart1_device;
+                               at91_clock_associate("usart1_clk", 
&at91sam9rl_uart1_device.dev, "usart");
+                               break;
+                       case 2:
+                               configure_usart2_pins();
+                               at91_uarts[i] = &at91sam9rl_uart2_device;
+                               at91_clock_associate("usart2_clk", 
&at91sam9rl_uart2_device.dev, "usart");
+                               break;
+                       case 3:
+                               configure_usart3_pins();
+                               at91_uarts[i] = &at91sam9rl_uart3_device;
+                               at91_clock_associate("usart3_clk", 
&at91sam9rl_uart3_device.dev, "usart");
+                               break;
+                       case 4:
+                               configure_dbgu_pins();
+                               at91_uarts[i] = &at91sam9rl_dbgu_device;
+                               at91_clock_associate("mck", 
&at91sam9rl_dbgu_device.dev, "usart");
+                               break;
+                       default:
+                               continue;
+               }
+               at91_uarts[i]->id = i;          /* update ID number to mapped 
ID */
+       }
+
+       /* Set serial console device */
+       if (config->console_tty < ATMEL_MAX_UART)
+               atmel_default_console_device = at91_uarts[config->console_tty];
+       if (!atmel_default_console_device)
+               printk(KERN_INFO "AT91: No default serial console defined.\n");
+}
+
+void __init at91_add_device_serial(void)
+{
+       int i;
+
+       for (i = 0; i < ATMEL_MAX_UART; i++) {
+               if (at91_uarts[i])
+                       platform_device_register(at91_uarts[i]);
+       }
+}
+#else
+void __init at91_init_serial(struct at91_uart_config *config) {}
+void __init at91_add_device_serial(void) {}
+#endif
+
+
+/* -------------------------------------------------------------------- */
+
+/*
+ * These devices are always present and don't need any board-specific
+ * setup.
+ */
+static int __init at91_add_standard_devices(void)
+{
+       return 0;
+}
+
+arch_initcall(at91_add_standard_devices);
diff --git a/arch/arm/mach-at91/generic.h b/arch/arm/mach-at91/generic.h
index bda2622..68ed71a 100644
--- a/arch/arm/mach-at91/generic.h
+++ b/arch/arm/mach-at91/generic.h
@@ -13,12 +13,14 @@ extern void __init at91rm9200_initialize(unsigned long 
main_clock, unsigned shor
 extern void __init at91sam9260_initialize(unsigned long main_clock);
 extern void __init at91sam9261_initialize(unsigned long main_clock);
 extern void __init at91sam9263_initialize(unsigned long main_clock);
+extern void __init at91sam9rl_initialize(unsigned long main_clock);
 
  /* Interrupts */
 extern void __init at91rm9200_init_interrupts(unsigned int priority[]);
 extern void __init at91sam9260_init_interrupts(unsigned int priority[]);
 extern void __init at91sam9261_init_interrupts(unsigned int priority[]);
 extern void __init at91sam9263_init_interrupts(unsigned int priority[]);
+extern void __init at91sam9rl_init_interrupts(unsigned int priority[]);
 extern void __init at91_aic_init(unsigned int priority[]);
 
  /* Timer */
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index 2900e59..b8320a1 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -171,8 +171,8 @@ config CPU_ARM925T
 # ARM926T
 config CPU_ARM926T
        bool "Support ARM926T processor"
-       depends on ARCH_INTEGRATOR || ARCH_VERSATILE_PB || MACH_VERSATILE_AB || 
ARCH_OMAP730 || ARCH_OMAP16XX || MACH_REALVIEW_EB || ARCH_PNX4008 || ARCH_NETX 
|| CPU_S3C2412 || ARCH_AT91SAM9260 || ARCH_AT91SAM9261 || ARCH_AT91SAM9263 || 
ARCH_NS9XXX || ARCH_DAVINCI
-       default y if ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || 
ARCH_OMAP16XX || ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || ARCH_AT91SAM9260 
|| ARCH_AT91SAM9261 || ARCH_AT91SAM9263 || ARCH_NS9XXX || ARCH_DAVINCI
+       depends on ARCH_INTEGRATOR || ARCH_VERSATILE_PB || MACH_VERSATILE_AB || 
ARCH_OMAP730 || ARCH_OMAP16XX || MACH_REALVIEW_EB || ARCH_PNX4008 || ARCH_NETX 
|| CPU_S3C2412 || ARCH_AT91SAM9260 || ARCH_AT91SAM9261 || ARCH_AT91SAM9263 || 
ARCH_AT91SAM9RL || ARCH_NS9XXX || ARCH_DAVINCI
+       default y if ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || 
ARCH_OMAP16XX || ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || ARCH_AT91SAM9260 
|| ARCH_AT91SAM9261 || ARCH_AT91SAM9263 || ARCH_AT91SAM9RL || ARCH_NS9XXX || 
ARCH_DAVINCI
        select CPU_32v5
        select CPU_ABRT_EV5TJ
        select CPU_CACHE_VIVT
diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig
index 8065f2b..f771a7c 100644
--- a/drivers/usb/gadget/Kconfig
+++ b/drivers/usb/gadget/Kconfig
@@ -210,7 +210,7 @@ config USB_OTG
 
 config USB_GADGET_AT91
        boolean "AT91 USB Device Port"
-       depends on ARCH_AT91
+       depends on ARCH_AT91 && !ARCH_AT91SAM9RL
        select USB_GADGET_SELECTED
        help
           Many Atmel AT91 processors (such as the AT91RM2000) have a
diff --git a/include/asm-arm/arch-at91/at91sam9rl.h 
b/include/asm-arm/arch-at91/at91sam9rl.h
new file mode 100644
index 0000000..8a9708a
--- /dev/null
+++ b/include/asm-arm/arch-at91/at91sam9rl.h
@@ -0,0 +1,110 @@
+/*
+ * include/asm-arm/arch-at91/at91sam9260.h
+ *
+ *  Copyright (C) 2007 Atmel Corporation
+ *
+ * Common definitions.
+ * Based on AT91SAM9RL datasheet revision A. (Preliminary)
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file COPYING in the main directory of this archive for
+ * more details.
+ */
+
+#ifndef AT91SAM9RL_H
+#define AT91SAM9RL_H
+
+/*
+ * Peripheral identifiers/interrupts.
+ */
+#define AT91_ID_FIQ            0       /* Advanced Interrupt Controller (FIQ) 
*/
+#define AT91_ID_SYS            1       /* System Controller */
+#define AT91SAM9RL_ID_PIOA     2       /* Parallel IO Controller A */
+#define AT91SAM9RL_ID_PIOB     3       /* Parallel IO Controller B */
+#define AT91SAM9RL_ID_PIOC     4       /* Parallel IO Controller C */
+#define AT91SAM9RL_ID_PIOD     5       /* Parallel IO Controller D */
+#define AT91SAM9RL_ID_US0      6       /* USART 0 */
+#define AT91SAM9RL_ID_US1      7       /* USART 1 */
+#define AT91SAM9RL_ID_US2      8       /* USART 2 */
+#define AT91SAM9RL_ID_US3      9       /* USART 3 */
+#define AT91SAM9RL_ID_MCI      10      /* Multimedia Card Interface */
+#define AT91SAM9RL_ID_TWI0     11      /* TWI 0 */
+#define AT91SAM9RL_ID_TWI1     12      /* TWI 1 */
+#define AT91SAM9RL_ID_SPI      13      /* Serial Peripheral Interface */
+#define AT91SAM9RL_ID_SSC0     14      /* Serial Synchronous Controller 0 */
+#define AT91SAM9RL_ID_SSC1     15      /* Serial Synchronous Controller 1 */
+#define AT91SAM9RL_ID_TC0      16      /* Timer Counter 0 */
+#define AT91SAM9RL_ID_TC1      17      /* Timer Counter 1 */
+#define AT91SAM9RL_ID_TC2      18      /* Timer Counter 2 */
+#define AT91SAM9RL_ID_PWMC     19      /* Pulse Width Modulation Controller */
+#define AT91SAM9RL_ID_TSC      20      /* Touch Screen Controller */
+#define AT91SAM9RL_ID_DMA      21      /* DMA Controller */
+#define AT91SAM9RL_ID_UDPHS    22      /* USB Device HS */
+#define AT91SAM9RL_ID_LCDC     23      /* LCD Controller */
+#define AT91SAM9RL_ID_AC97C    24      /* AC97 Controller */
+#define AT91SAM9RL_ID_IRQ0     31      /* Advanced Interrupt Controller (IRQ0) 
*/
+
+
+/*
+ * User Peripheral physical base addresses.
+ */
+#define AT91SAM9RL_BASE_TCB0   0xfffa0000
+#define AT91SAM9RL_BASE_TC0    0xfffa0000
+#define AT91SAM9RL_BASE_TC1    0xfffa0040
+#define AT91SAM9RL_BASE_TC2    0xfffa0080
+#define AT91SAM9RL_BASE_MCI    0xfffa4000
+#define AT91SAM9RL_BASE_TWI0   0xfffa8000
+#define AT91SAM9RL_BASE_TWI1   0xfffac000
+#define AT91SAM9RL_BASE_US0    0xfffb0000
+#define AT91SAM9RL_BASE_US1    0xfffb4000
+#define AT91SAM9RL_BASE_US2    0xfffb8000
+#define AT91SAM9RL_BASE_US3    0xfffbc000
+#define AT91SAM9RL_BASE_SSC0   0xfffc0000
+#define AT91SAM9RL_BASE_SSC1   0xfffc4000
+#define AT91SAM9RL_BASE_PWMC   0xfffc8000
+#define AT91SAM9RL_BASE_SPI    0xfffcc000
+#define AT91SAM9RL_BASE_TSC    0xfffd0000
+#define AT91SAM9RL_BASE_UDPHS  0xfffd4000
+#define AT91SAM9RL_BASE_AC97C  0xfffd8000
+#define AT91_BASE_SYS          0xffffc000
+
+
+/*
+ * System Peripherals (offset from AT91_BASE_SYS)
+ */
+#define AT91_DMA       (0xffffe600 - AT91_BASE_SYS)
+#define AT91_ECC       (0xffffe800 - AT91_BASE_SYS)
+#define AT91_SDRAMC    (0xffffea00 - AT91_BASE_SYS)
+#define AT91_SMC       (0xffffec00 - AT91_BASE_SYS)
+#define AT91_MATRIX    (0xffffee00 - AT91_BASE_SYS)
+#define AT91_CCFG      (0xffffef10 - AT91_BASE_SYS)
+#define AT91_AIC       (0xfffff000 - AT91_BASE_SYS)
+#define AT91_DBGU      (0xfffff200 - AT91_BASE_SYS)
+#define AT91_PIOA      (0xfffff400 - AT91_BASE_SYS)
+#define AT91_PIOB      (0xfffff600 - AT91_BASE_SYS)
+#define AT91_PIOC      (0xfffff800 - AT91_BASE_SYS)
+#define AT91_PIOD      (0xfffffa00 - AT91_BASE_SYS)
+#define AT91_PMC       (0xfffffc00 - AT91_BASE_SYS)
+#define AT91_RSTC      (0xfffffd00 - AT91_BASE_SYS)
+#define AT91_SHDWC     (0xfffffd10 - AT91_BASE_SYS)
+#define AT91_RTT       (0xfffffd20 - AT91_BASE_SYS)
+#define AT91_PIT       (0xfffffd30 - AT91_BASE_SYS)
+#define AT91_WDT       (0xfffffd40 - AT91_BASE_SYS)
+#define AT91_SCKCR     (0xfffffd50 - AT91_BASE_SYS)
+#define AT91_GPBR      (0xfffffd60 - AT91_BASE_SYS)
+#define AT91_RTC       (0xfffffe00 - AT91_BASE_SYS)
+
+
+/*
+ * Internal Memory.
+ */
+#define AT91SAM9RL_SRAM_BASE   0x00300000      /* Internal SRAM base address */
+#define AT91SAM9RL_SRAM_SIZE   SZ_16K          /* Internal SRAM size (16Kb) */
+
+#define AT91SAM9RL_ROM_BASE    0x00400000      /* Internal ROM base address */
+#define AT91SAM9RL_ROM_SIZE    (2 * SZ_16K)    /* Internal ROM size (32Kb) */
+
+#define AT91SAM9RL_LCDC_BASE   0x00500000      /* LCD Controller */
+#define AT91SAM9RL_UDPHS_BASE  0x00600000      /* USB Device HS controller */
+
+#endif
diff --git a/include/asm-arm/arch-at91/at91sam9rl_matrix.h 
b/include/asm-arm/arch-at91/at91sam9rl_matrix.h
new file mode 100644
index 0000000..b15f11b
--- /dev/null
+++ b/include/asm-arm/arch-at91/at91sam9rl_matrix.h
@@ -0,0 +1,96 @@
+/*
+ * include/asm-arm/arch-at91/at91sam9rl_matrix.h
+ *
+ *  Copyright (C) 2007 Atmel Corporation
+ *
+ * Memory Controllers (MATRIX, EBI) - System peripherals registers.
+ * Based on AT91SAM9RL datasheet revision A. (Preliminary)
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file COPYING in the main directory of this archive for
+ * more details.
+ */
+
+#ifndef AT91SAM9RL_MATRIX_H
+#define AT91SAM9RL_MATRIX_H
+
+#define AT91_MATRIX_MCFG0      (AT91_MATRIX + 0x00)    /* Master Configuration 
Register 0 */
+#define AT91_MATRIX_MCFG1      (AT91_MATRIX + 0x04)    /* Master Configuration 
Register 1 */
+#define AT91_MATRIX_MCFG2      (AT91_MATRIX + 0x08)    /* Master Configuration 
Register 2 */
+#define AT91_MATRIX_MCFG3      (AT91_MATRIX + 0x0C)    /* Master Configuration 
Register 3 */
+#define AT91_MATRIX_MCFG4      (AT91_MATRIX + 0x10)    /* Master Configuration 
Register 4 */
+#define AT91_MATRIX_MCFG5      (AT91_MATRIX + 0x14)    /* Master Configuration 
Register 5 */
+#define                AT91_MATRIX_ULBT        (7 << 0)        /* Undefined 
Length Burst Type */
+#define                        AT91_MATRIX_ULBT_INFINITE       (0 << 0)
+#define                        AT91_MATRIX_ULBT_SINGLE         (1 << 0)
+#define                        AT91_MATRIX_ULBT_FOUR           (2 << 0)
+#define                        AT91_MATRIX_ULBT_EIGHT          (3 << 0)
+#define                        AT91_MATRIX_ULBT_SIXTEEN        (4 << 0)
+
+#define AT91_MATRIX_SCFG0      (AT91_MATRIX + 0x40)    /* Slave Configuration 
Register 0 */
+#define AT91_MATRIX_SCFG1      (AT91_MATRIX + 0x44)    /* Slave Configuration 
Register 1 */
+#define AT91_MATRIX_SCFG2      (AT91_MATRIX + 0x48)    /* Slave Configuration 
Register 2 */
+#define AT91_MATRIX_SCFG3      (AT91_MATRIX + 0x4C)    /* Slave Configuration 
Register 3 */
+#define AT91_MATRIX_SCFG4      (AT91_MATRIX + 0x50)    /* Slave Configuration 
Register 4 */
+#define AT91_MATRIX_SCFG5      (AT91_MATRIX + 0x54)    /* Slave Configuration 
Register 5 */
+#define                AT91_MATRIX_SLOT_CYCLE          (0xff << 0)     /* 
Maximum Number of Allowed Cycles for a Burst */
+#define                AT91_MATRIX_DEFMSTR_TYPE        (3    << 16)    /* 
Default Master Type */
+#define                        AT91_MATRIX_DEFMSTR_TYPE_NONE   (0 << 16)
+#define                        AT91_MATRIX_DEFMSTR_TYPE_LAST   (1 << 16)
+#define                        AT91_MATRIX_DEFMSTR_TYPE_FIXED  (2 << 16)
+#define                AT91_MATRIX_FIXED_DEFMSTR       (7    << 18)    /* 
Fixed Index of Default Master */
+#define                AT91_MATRIX_ARBT                (3    << 24)    /* 
Arbitration Type */
+#define                        AT91_MATRIX_ARBT_ROUND_ROBIN    (0 << 24)
+#define                        AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24)
+
+#define AT91_MATRIX_PRAS0      (AT91_MATRIX + 0x80)    /* Priority Register A 
for Slave 0 */
+#define AT91_MATRIX_PRAS1      (AT91_MATRIX + 0x88)    /* Priority Register A 
for Slave 1 */
+#define AT91_MATRIX_PRAS2      (AT91_MATRIX + 0x90)    /* Priority Register A 
for Slave 2 */
+#define AT91_MATRIX_PRAS3      (AT91_MATRIX + 0x98)    /* Priority Register A 
for Slave 3 */
+#define AT91_MATRIX_PRAS4      (AT91_MATRIX + 0xA0)    /* Priority Register A 
for Slave 4 */
+#define AT91_MATRIX_PRAS5      (AT91_MATRIX + 0xA8)    /* Priority Register A 
for Slave 5 */
+#define                AT91_MATRIX_M0PR                (3 << 0)        /* 
Master 0 Priority */
+#define                AT91_MATRIX_M1PR                (3 << 4)        /* 
Master 1 Priority */
+#define                AT91_MATRIX_M2PR                (3 << 8)        /* 
Master 2 Priority */
+#define                AT91_MATRIX_M3PR                (3 << 12)       /* 
Master 3 Priority */
+#define                AT91_MATRIX_M4PR                (3 << 16)       /* 
Master 4 Priority */
+#define                AT91_MATRIX_M5PR                (3 << 20)       /* 
Master 5 Priority */
+
+#define AT91_MATRIX_MRCR       (AT91_MATRIX + 0x100)   /* Master Remap Control 
Register */
+#define                AT91_MATRIX_RCB0                (1 << 0)        /* 
Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
+#define                AT91_MATRIX_RCB1                (1 << 1)        /* 
Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
+#define                AT91_MATRIX_RCB2                (1 << 2)
+#define                AT91_MATRIX_RCB3                (1 << 3)
+#define                AT91_MATRIX_RCB4                (1 << 4)
+#define                AT91_MATRIX_RCB5                (1 << 5)
+
+#define AT91_MATRIX_TCMR       (AT91_MATRIX + 0x114)   /* TCM Configuration 
Register */
+#define                AT91_MATRIX_ITCM_SIZE           (0xf << 0)      /* Size 
of ITCM enabled memory block */
+#define                        AT91_MATRIX_ITCM_0              (0 << 0)
+#define                        AT91_MATRIX_ITCM_16             (5 << 0)
+#define                        AT91_MATRIX_ITCM_32             (6 << 0)
+#define                AT91_MATRIX_DTCM_SIZE           (0xf << 4)      /* Size 
of DTCM enabled memory block */
+#define                        AT91_MATRIX_DTCM_0              (0 << 4)
+#define                        AT91_MATRIX_DTCM_16             (5 << 4)
+#define                        AT91_MATRIX_DTCM_32             (6 << 4)
+
+#define AT91_MATRIX_EBICSA     (AT91_MATRIX + 0x120)   /* EBI0 Chip Select 
Assignment Register */
+#define                AT91_MATRIX_CS1A                (1 << 1)        /* Chip 
Select 1 Assignment */
+#define                        AT91_MATRIX_CS1A_SMC            (0 << 1)
+#define                        AT91_MATRIX_CS1A_SDRAMC         (1 << 1)
+#define                AT91_MATRIX_CS3A                (1 << 3)        /* Chip 
Select 3 Assignment */
+#define                        AT91_MATRIX_CS3A_SMC            (0 << 3)
+#define                        AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3)
+#define                AT91_MATRIX_CS4A                (1 << 4)        /* Chip 
Select 4 Assignment */
+#define                        AT91_MATRIX_CS4A_SMC            (0 << 4)
+#define                        AT91_MATRIX_CS4A_SMC_CF1        (1 << 4)
+#define                AT91_MATRIX_CS5A                (1 << 5)        /* Chip 
Select 5 Assignment */
+#define                        AT91_MATRIX_CS5A_SMC            (0 << 5)
+#define                        AT91_MATRIX_CS5A_SMC_CF2        (1 << 5)
+#define                AT91_MATRIX_DBPUC               (1 << 8)        /* Data 
Bus Pull-up Configuration */
+#define                AT91_MATRIX_VDDIOMSEL           (1 << 16)       /* 
Memory voltage selection */
+#define                        AT91_MATRIX_VDDIOMSEL_1_8V      (0 << 16)
+#define                        AT91_MATRIX_VDDIOMSEL_3_3V      (1 << 16)
+
+
+#endif
diff --git a/include/asm-arm/arch-at91/cpu.h b/include/asm-arm/arch-at91/cpu.h
index 7ef4eeb..ef93c30 100644
--- a/include/asm-arm/arch-at91/cpu.h
+++ b/include/asm-arm/arch-at91/cpu.h
@@ -26,6 +26,8 @@
 #define ARCH_ID_AT91SAM9XE256  0x329a93a0
 #define ARCH_ID_AT91SAM9XE512  0x329aa3a0
 
+#define ARCH_ID_AT91SAM9RL64   0x019b03a0
+
 static inline unsigned long at91_cpu_identify(void)
 {
        return (at91_sys_read(AT91_DBGU_CIDR) & ~AT91_CIDR_VERSION);
@@ -68,6 +70,13 @@ static inline unsigned long at91_arch_identify(void)
 #define cpu_is_at91sam9263()   (0)
 #endif
 
+#ifdef CONFIG_ARCH_AT91SAM9RL
+#define cpu_is_at91sam9rl()    (at91_cpu_identify() == ARCH_ID_AT91SAM9RL64)
+#else
+#define cpu_is_at91sam9rl()    (0)
+#endif
+
+
 /*
  * Since this is ARM, we will never run on any AVR32 CPU. But these
  * definitions may reduce clutter in common drivers.
diff --git a/include/asm-arm/arch-at91/hardware.h 
b/include/asm-arm/arch-at91/hardware.h
index 28133e0..0e51ad2 100644
--- a/include/asm-arm/arch-at91/hardware.h
+++ b/include/asm-arm/arch-at91/hardware.h
@@ -24,6 +24,8 @@
 #include <asm/arch/at91sam9261.h>
 #elif defined(CONFIG_ARCH_AT91SAM9263)
 #include <asm/arch/at91sam9263.h>
+#elif defined(CONFIG_ARCH_AT91SAM9RL)
+#include <asm/arch/at91sam9rl.h>
 #else
 #error "Unsupported AT91 processor"
 #endif
diff --git a/include/asm-arm/arch-at91/timex.h 
b/include/asm-arm/arch-at91/timex.h
index f41636d..2df1ee1 100644
--- a/include/asm-arm/arch-at91/timex.h
+++ b/include/asm-arm/arch-at91/timex.h
@@ -37,6 +37,11 @@
 #define AT91SAM9_MASTER_CLOCK  99959500
 #define CLOCK_TICK_RATE                (AT91SAM9_MASTER_CLOCK/16)
 
+#elif defined(CONFIG_ARCH_AT91SAM9RL)
+
+#define AT91SAM9_MASTER_CLOCK  100000000
+#define CLOCK_TICK_RATE                (AT91SAM9_MASTER_CLOCK/16)
+
 #endif
 
 #endif
diff --git a/include/asm-avr32/arch-at32ap/cpu.h 
b/include/asm-avr32/arch-at32ap/cpu.h
index 2bdc5bd..a762f42 100644
--- a/include/asm-avr32/arch-at32ap/cpu.h
+++ b/include/asm-avr32/arch-at32ap/cpu.h
@@ -29,5 +29,6 @@
 #define cpu_is_at91sam9260()   (0)
 #define cpu_is_at91sam9261()   (0)
 #define cpu_is_at91sam9263()   (0)
+#define cpu_is_at91sam9rl()    (0)
 
 #endif /* __ASM_ARCH_CPU_H */
-
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