Gitweb:
http://git.kernel.org/git/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commit;h=6ba07e590d1f841a5d0539978399b852a015ab53
Commit: 6ba07e590d1f841a5d0539978399b852a015ab53
Parent: 490dcc4d309141b622107ad5ad82674a01e089bc
Author: Atsushi Nemoto <[EMAIL PROTECTED]>
AuthorDate: Mon May 21 23:45:38 2007 +0900
Committer: Ralf Baechle <[EMAIL PROTECTED]>
CommitDate: Wed Jun 6 19:34:33 2007 +0100
[MIPS] Fix warning by moving do_default_vi into CONFIG_CPU_MIPSR2_SRS
This fixes the warning:
arch/mips/kernel/traps.c:931: warning: 'do_default_vi' defined but not used
Signed-off-by: Atsushi Nemoto <[EMAIL PROTECTED]>
Signed-off-by: Ralf Baechle <[EMAIL PROTECTED]>
---
arch/mips/kernel/traps.c | 12 ++++++------
1 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index 200de02..3f58b6a 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -927,12 +927,6 @@ asmlinkage void do_reserved(struct pt_regs *regs)
(regs->cp0_cause & 0x7f) >> 2);
}
-static asmlinkage void do_default_vi(void)
-{
- show_regs(get_irq_regs());
- panic("Caught unexpected vectored interrupt.");
-}
-
/*
* Some MIPS CPUs can enable/disable for cache parity detection, but do
* it different ways.
@@ -1128,6 +1122,12 @@ void mips_srs_free(int set)
clear_bit(set, &sr->sr_allocated);
}
+static asmlinkage void do_default_vi(void)
+{
+ show_regs(get_irq_regs());
+ panic("Caught unexpected vectored interrupt.");
+}
+
static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs)
{
unsigned long handler;
-
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