Gitweb:     
http://git.kernel.org/git/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commit;h=8006bf56e360a4db71d304df778870a371a9e930
Commit:     8006bf56e360a4db71d304df778870a371a9e930
Parent:     52374f890c1d0d64148d55a20d995a0b3e0ae987
Author:     Albert Lee <[EMAIL PROTECTED]>
AuthorDate: Tue Jul 3 22:28:36 2007 +0200
Committer:  Bartlomiej Zolnierkiewicz <[EMAIL PROTECTED]>
CommitDate: Tue Jul 3 22:28:36 2007 +0200

    ide: pdc202xx_new PLL input clock fix
    
    Recently the PLL input clock of Promise 2027x is sometimes detected
    higher than expected (e.g. 20.027 MHz compared to 16.714 MHz).
    It seems sometimes the mdelay() function is not as precise as it
    used to be. Per Alan's advice, HT or power management might affect
    the precision of mdelay().
    
    This patch calls gettimeofday() to measure the time elapsed and
    calculate the PLL input clock accordingly.
    
    Signed-off-by: Albert Lee <[EMAIL PROTECTED]>
    Cc: Alan Cox <[EMAIL PROTECTED]>
    Cc: Bahadir Balban <[EMAIL PROTECTED]>
    Acked-by: Sergei Shtylyov <[EMAIL PROTECTED]>
    Signed-off-by: Bartlomiej Zolnierkiewicz <[EMAIL PROTECTED]>
---
 drivers/ide/pci/pdc202xx_new.c |   10 ++++++++--
 1 files changed, 8 insertions(+), 2 deletions(-)

diff --git a/drivers/ide/pci/pdc202xx_new.c b/drivers/ide/pci/pdc202xx_new.c
index cc0bfdc..0765dce 100644
--- a/drivers/ide/pci/pdc202xx_new.c
+++ b/drivers/ide/pci/pdc202xx_new.c
@@ -306,11 +306,13 @@ static long __devinit read_counter(u32 dma_base)
  */
 static long __devinit detect_pll_input_clock(unsigned long dma_base)
 {
+       struct timeval start_time, end_time;
        long start_count, end_count;
-       long pll_input;
+       long pll_input, usec_elapsed;
        u8 scr1;
 
        start_count = read_counter(dma_base);
+       do_gettimeofday(&start_time);
 
        /* Start the test mode */
        outb(0x01, dma_base + 0x01);
@@ -322,6 +324,7 @@ static long __devinit detect_pll_input_clock(unsigned long 
dma_base)
        mdelay(10);
 
        end_count = read_counter(dma_base);
+       do_gettimeofday(&end_time);
 
        /* Stop the test mode */
        outb(0x01, dma_base + 0x01);
@@ -333,7 +336,10 @@ static long __devinit detect_pll_input_clock(unsigned long 
dma_base)
         * Calculate the input clock in Hz
         * (the clock counter is 30 bit wide and counts down)
         */
-       pll_input = ((start_count - end_count) & 0x3ffffff) * 100;
+       usec_elapsed = (end_time.tv_sec - start_time.tv_sec) * 1000000 +
+               (end_time.tv_usec - start_time.tv_usec);
+       pll_input = ((start_count - end_count) & 0x3ffffff) / 10 *
+               (10000000 / usec_elapsed);
 
        DBG("start[%ld] end[%ld]\n", start_count, end_count);
 
-
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