Gitweb:     
http://git.kernel.org/git/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commit;h=4b3e975e4a06f1710693c5aa51b8f98facfa9863
Commit:     4b3e975e4a06f1710693c5aa51b8f98facfa9863
Parent:     fde97822a295da9dffa4af643b49a58ffc4516ad
Author:     Ralf Baechle <[EMAIL PROTECTED]>
AuthorDate: Thu Jun 21 00:22:34 2007 +0100
Committer:  Ralf Baechle <[EMAIL PROTECTED]>
CommitDate: Fri Jul 6 16:17:11 2007 +0100

    [MIPS] Fix scheduling latency issue on 24K, 34K and 74K cores
    
    The idle loop goes to sleep using the WAIT instruction if !need_resched().
    This has is suffering from from a race condition that if if just after
    need_resched has returned 0 an interrupt might set TIF_NEED_RESCHED but
    we've just completed the test so go to sleep anyway.  This would be
    trivial to fix by just disabling interrupts during that sequence as in:
    
            local_irq_disable();
            if (!need_resched())
                    __asm__("wait");
            local_irq_enable();
    
    but the processor architecture leaves it undefined if a processor calling
    WAIT with interrupts disabled will ever restart its pipeline and indeed
    some processors have made use of the freedom provided by the architecture
    definition.  This has been resolved and the Config7.WII bit indicates that
    the use of WAIT is safe on 24K, 24KE and 34K cores.  It also is safe on
    74K starting revision 2.1.0 so enable the use of WAIT with interrupts
    disabled for 74K based on a c0_prid of at least that.
    
    Signed-off-by: Ralf Baechle <[EMAIL PROTECTED]>
---
 arch/mips/kernel/cpu-probe.c |   15 +++++++++++++--
 include/asm-mips/mipsregs.h  |    2 ++
 2 files changed, 15 insertions(+), 2 deletions(-)

diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index 0fc90ba..b12eeee 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -137,13 +137,24 @@ static inline void check_wait(void)
        case CPU_4KEC:
        case CPU_4KSC:
        case CPU_5KC:
-       case CPU_24K:
        case CPU_25KF:
+       case CPU_PR4450:
+               cpu_wait = r4k_wait;
+               break;
+
+       case CPU_24K:
        case CPU_34K:
+               cpu_wait = r4k_wait;
+               if (read_c0_config7() & MIPS_CONF7_WII)
+                       cpu_wait = r4k_wait_irqoff;
+               break;
+
        case CPU_74K:
-       case CPU_PR4450:
                cpu_wait = r4k_wait;
+               if ((c->processor_id & 0xff) >= PRID_REV_ENCODE_332(2, 1, 0))
+                       cpu_wait = r4k_wait_irqoff;
                break;
+
        case CPU_TX49XX:
                cpu_wait = r4k_wait_irqoff;
                break;
diff --git a/include/asm-mips/mipsregs.h b/include/asm-mips/mipsregs.h
index 9985cb7..89c8192 100644
--- a/include/asm-mips/mipsregs.h
+++ b/include/asm-mips/mipsregs.h
@@ -534,6 +534,8 @@
 #define MIPS_CONF3_LPA         (_ULCAST_(1) <<  7)
 #define MIPS_CONF3_DSP         (_ULCAST_(1) << 10)
 
+#define MIPS_CONF7_WII         (_ULCAST_(1) << 31)
+
 /*
  * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register.
  */
-
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