Gitweb:     
http://git.kernel.org/git/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commit;h=fde97822a295da9dffa4af643b49a58ffc4516ad
Commit:     fde97822a295da9dffa4af643b49a58ffc4516ad
Parent:     075c733e19ce7530b53b78151cc4d303c8f64548
Author:     Ralf Baechle <[EMAIL PROTECTED]>
AuthorDate: Fri Jul 6 14:40:05 2007 +0100
Committer:  Ralf Baechle <[EMAIL PROTECTED]>
CommitDate: Fri Jul 6 16:17:11 2007 +0100

    [MIPS] Add macros to encode processor revisions.
    
    Older processors used to encode processor version and revision in two
    4-bit bitfields, the 4K seems to simply count up and even newer MTI cores
    have switched to use the 8-bits as 3:3:2 bitfield with the last field as
    the patch number.
    
    Signed-off-by: Ralf Baechle <[EMAIL PROTECTED]>
---
 include/asm-mips/cpu.h |   11 +++++++++++
 1 files changed, 11 insertions(+), 0 deletions(-)

diff --git a/include/asm-mips/cpu.h b/include/asm-mips/cpu.h
index d38fdbf..2924069 100644
--- a/include/asm-mips/cpu.h
+++ b/include/asm-mips/cpu.h
@@ -125,6 +125,17 @@
 #define PRID_REV_VR4130                0x0080
 
 /*
+ * Older processors used to encode processor version and revision in two
+ * 4-bit bitfields, the 4K seems to simply count up and even newer MTI cores
+ * have switched to use the 8-bits as 3:3:2 bitfield with the last field as
+ * the patch number.  *ARGH*
+ */
+#define PRID_REV_ENCODE_44(ver, rev)                                   \
+       ((ver) << 4 | (rev))
+#define PRID_REV_ENCODE_332(ver, rev, patch)                           \
+       ((ver) << 5 | (rev) << 2 | (patch))
+
+/*
  * FPU implementation/revision register (CP1 control register 0).
  *
  * +---------------------------------+----------------+----------------+
-
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