Gitweb:     
http://git.kernel.org/git/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commit;h=3120234551ebf5f6e24a23082334eb3897b5db41
Commit:     3120234551ebf5f6e24a23082334eb3897b5db41
Parent:     67f74c9d223815e30eac456b4956a846143b65c6
Author:     David Gibson <[EMAIL PROTECTED]>
AuthorDate: Fri Jun 22 14:58:55 2007 +1000
Committer:  Kumar Gala <[EMAIL PROTECTED]>
CommitDate: Tue Jul 3 03:00:28 2007 -0500

    [POWERPC] Split out asm-ppc/mmu.h portions for PowerPC 8xx
    
    arch/powerpc still relies on asm-ppc/mmu.h for some 32-bit MMU types.
    This patch is another step towards fixing this.  It takes the portions
    of asm-ppc/mmu.h related to 8xx embedded CPUs which are still relevant
    in arch/powerpc and puts them in a new asm-powerpc/mmu-8xx.h,
    included when appropriate from asm-powerpc/mmu.h.
    
    Signed-off-by: David Gibson <[EMAIL PROTECTED]>
    Signed-off-by: Kumar Gala <[EMAIL PROTECTED]>
---
 include/asm-powerpc/mmu-8xx.h |  147 +++++++++++++++++++++++++++++++++++++++++
 include/asm-powerpc/mmu.h     |    7 +-
 2 files changed, 150 insertions(+), 4 deletions(-)

diff --git a/include/asm-powerpc/mmu-8xx.h b/include/asm-powerpc/mmu-8xx.h
new file mode 100644
index 0000000..952bd88
--- /dev/null
+++ b/include/asm-powerpc/mmu-8xx.h
@@ -0,0 +1,147 @@
+#ifndef _ASM_POWERPC_MMU_8XX_H_
+#define _ASM_POWERPC_MMU_8XX_H_
+/*
+ * PPC8xx support
+ */
+
+/* Control/status registers for the MPC8xx.
+ * A write operation to these registers causes serialized access.
+ * During software tablewalk, the registers used perform mask/shift-add
+ * operations when written/read.  A TLB entry is created when the Mx_RPN
+ * is written, and the contents of several registers are used to
+ * create the entry.
+ */
+#define SPRN_MI_CTR    784     /* Instruction TLB control register */
+#define MI_GPM         0x80000000      /* Set domain manager mode */
+#define MI_PPM         0x40000000      /* Set subpage protection */
+#define MI_CIDEF       0x20000000      /* Set cache inhibit when MMU dis */
+#define MI_RSV4I       0x08000000      /* Reserve 4 TLB entries */
+#define MI_PPCS                0x02000000      /* Use MI_RPN prob/priv state */
+#define MI_IDXMASK     0x00001f00      /* TLB index to be loaded */
+#define MI_RESETVAL    0x00000000      /* Value of register at reset */
+
+/* These are the Ks and Kp from the PowerPC books.  For proper operation,
+ * Ks = 0, Kp = 1.
+ */
+#define SPRN_MI_AP     786
+#define MI_Ks          0x80000000      /* Should not be set */
+#define MI_Kp          0x40000000      /* Should always be set */
+
+/* The effective page number register.  When read, contains the information
+ * about the last instruction TLB miss.  When MI_RPN is written, bits in
+ * this register are used to create the TLB entry.
+ */
+#define SPRN_MI_EPN    787
+#define MI_EPNMASK     0xfffff000      /* Effective page number for entry */
+#define MI_EVALID      0x00000200      /* Entry is valid */
+#define MI_ASIDMASK    0x0000000f      /* ASID match value */
+                                       /* Reset value is undefined */
+
+/* A "level 1" or "segment" or whatever you want to call it register.
+ * For the instruction TLB, it contains bits that get loaded into the
+ * TLB entry when the MI_RPN is written.
+ */
+#define SPRN_MI_TWC    789
+#define MI_APG         0x000001e0      /* Access protection group (0) */
+#define MI_GUARDED     0x00000010      /* Guarded storage */
+#define MI_PSMASK      0x0000000c      /* Mask of page size bits */
+#define MI_PS8MEG      0x0000000c      /* 8M page size */
+#define MI_PS512K      0x00000004      /* 512K page size */
+#define MI_PS4K_16K    0x00000000      /* 4K or 16K page size */
+#define MI_SVALID      0x00000001      /* Segment entry is valid */
+                                       /* Reset value is undefined */
+
+/* Real page number.  Defined by the pte.  Writing this register
+ * causes a TLB entry to be created for the instruction TLB, using
+ * additional information from the MI_EPN, and MI_TWC registers.
+ */
+#define SPRN_MI_RPN    790
+
+/* Define an RPN value for mapping kernel memory to large virtual
+ * pages for boot initialization.  This has real page number of 0,
+ * large page size, shared page, cache enabled, and valid.
+ * Also mark all subpages valid and write access.
+ */
+#define MI_BOOTINIT    0x000001fd
+
+#define SPRN_MD_CTR    792     /* Data TLB control register */
+#define MD_GPM         0x80000000      /* Set domain manager mode */
+#define MD_PPM         0x40000000      /* Set subpage protection */
+#define MD_CIDEF       0x20000000      /* Set cache inhibit when MMU dis */
+#define MD_WTDEF       0x10000000      /* Set writethrough when MMU dis */
+#define MD_RSV4I       0x08000000      /* Reserve 4 TLB entries */
+#define MD_TWAM                0x04000000      /* Use 4K page hardware assist 
*/
+#define MD_PPCS                0x02000000      /* Use MI_RPN prob/priv state */
+#define MD_IDXMASK     0x00001f00      /* TLB index to be loaded */
+#define MD_RESETVAL    0x04000000      /* Value of register at reset */
+
+#define SPRN_M_CASID   793     /* Address space ID (context) to match */
+#define MC_ASIDMASK    0x0000000f      /* Bits used for ASID value */
+
+
+/* These are the Ks and Kp from the PowerPC books.  For proper operation,
+ * Ks = 0, Kp = 1.
+ */
+#define SPRN_MD_AP     794
+#define MD_Ks          0x80000000      /* Should not be set */
+#define MD_Kp          0x40000000      /* Should always be set */
+
+/* The effective page number register.  When read, contains the information
+ * about the last instruction TLB miss.  When MD_RPN is written, bits in
+ * this register are used to create the TLB entry.
+ */
+#define SPRN_MD_EPN    795
+#define MD_EPNMASK     0xfffff000      /* Effective page number for entry */
+#define MD_EVALID      0x00000200      /* Entry is valid */
+#define MD_ASIDMASK    0x0000000f      /* ASID match value */
+                                       /* Reset value is undefined */
+
+/* The pointer to the base address of the first level page table.
+ * During a software tablewalk, reading this register provides the address
+ * of the entry associated with MD_EPN.
+ */
+#define SPRN_M_TWB     796
+#define        M_L1TB          0xfffff000      /* Level 1 table base address */
+#define M_L1INDX       0x00000ffc      /* Level 1 index, when read */
+                                       /* Reset value is undefined */
+
+/* A "level 1" or "segment" or whatever you want to call it register.
+ * For the data TLB, it contains bits that get loaded into the TLB entry
+ * when the MD_RPN is written.  It is also provides the hardware assist
+ * for finding the PTE address during software tablewalk.
+ */
+#define SPRN_MD_TWC    797
+#define MD_L2TB                0xfffff000      /* Level 2 table base address */
+#define MD_L2INDX      0xfffffe00      /* Level 2 index (*pte), when read */
+#define MD_APG         0x000001e0      /* Access protection group (0) */
+#define MD_GUARDED     0x00000010      /* Guarded storage */
+#define MD_PSMASK      0x0000000c      /* Mask of page size bits */
+#define MD_PS8MEG      0x0000000c      /* 8M page size */
+#define MD_PS512K      0x00000004      /* 512K page size */
+#define MD_PS4K_16K    0x00000000      /* 4K or 16K page size */
+#define MD_WT          0x00000002      /* Use writethrough page attribute */
+#define MD_SVALID      0x00000001      /* Segment entry is valid */
+                                       /* Reset value is undefined */
+
+
+/* Real page number.  Defined by the pte.  Writing this register
+ * causes a TLB entry to be created for the data TLB, using
+ * additional information from the MD_EPN, and MD_TWC registers.
+ */
+#define SPRN_MD_RPN    798
+
+/* This is a temporary storage register that could be used to save
+ * a processor working register during a tablewalk.
+ */
+#define SPRN_M_TW      799
+
+#ifndef __ASSEMBLY__
+typedef unsigned long phys_addr_t;
+
+typedef struct {
+       unsigned long id;
+       unsigned long vdso_base;
+} mm_context_t;
+#endif /* !__ASSEMBLY__ */
+
+#endif /* _ASM_POWERPC_MMU_8XX_H_ */
diff --git a/include/asm-powerpc/mmu.h b/include/asm-powerpc/mmu.h
index 9b71403..d44d211 100644
--- a/include/asm-powerpc/mmu.h
+++ b/include/asm-powerpc/mmu.h
@@ -14,10 +14,9 @@
 #elif defined(CONFIG_FSL_BOOKE)
 /* Freescale Book-E software loaded TLB */
 #  include <asm/mmu-fsl-booke.h>
-#else
-/* Other 32-bit.  FIXME: split up the other 32-bit MMU types, and
- * revise for arch/powerpc */
-#  include <asm-ppc/mmu.h>
+#elif defined (CONFIG_PPC_8xx)
+/* Motorola/Freescale 8xx software loaded TLB */
+#  include <asm/mmu-8xx.h>
 #endif
 
 #endif /* __KERNEL__ */
-
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