Gitweb:     
http://git.kernel.org/git/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commit;h=078f194045f892a10f4a5406e7cb06a7f8d42c57
Commit:     078f194045f892a10f4a5406e7cb06a7f8d42c57
Parent:     f5e6a280d153bff3b0cd15651d29d409f8dea698
Author:     will schmidt <[EMAIL PROTECTED]>
AuthorDate: Wed Jun 27 02:12:33 2007 +1000
Committer:  Paul Mackerras <[EMAIL PROTECTED]>
CommitDate: Tue Jul 10 21:55:48 2007 +1000

    [POWERPC] Oprofile enhanced instruction sampling support
    
    Oprofile enhanced instruction sampling support.
    
    When performing instruction sampling, the mmcra[SLOT] field can be used to
    more accurately identify the address of the sampled instruction.
    
    Tested on power4, js20, power5 and power5+.
    
    Signed-off-by: Will Schmidt <[EMAIL PROTECTED]>
    cc: Maynard Johnson <[EMAIL PROTECTED]>
    Signed-off-by: Paul Mackerras <[EMAIL PROTECTED]>
---
 arch/powerpc/oprofile/op_model_power4.c |   14 ++++++++++++++
 include/asm-powerpc/reg.h               |    2 ++
 2 files changed, 16 insertions(+), 0 deletions(-)

diff --git a/arch/powerpc/oprofile/op_model_power4.c 
b/arch/powerpc/oprofile/op_model_power4.c
index fe597a1..a7c206b 100644
--- a/arch/powerpc/oprofile/op_model_power4.c
+++ b/arch/powerpc/oprofile/op_model_power4.c
@@ -1,5 +1,7 @@
 /*
  * Copyright (C) 2004 Anton Blanchard <[EMAIL PROTECTED]>, IBM
+ * Added mmcra[slot] support:
+ * Copyright (C) 2006-2007 Will Schmidt <[EMAIL PROTECTED]>, IBM
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License
@@ -181,11 +183,17 @@ static void __attribute_used__ kernel_unknown_bucket(void)
  * On GQ and newer the MMCRA stores the HV and PR bits at the time
  * the SIAR was sampled. We use that to work out if the SIAR was sampled in
  * the hypervisor, our exception vectors or RTAS.
+ * If the MMCRA_SAMPLE_ENABLE bit is set, we can use the MMCRA[slot] bits
+ * to more accurately identify the address of the sampled instruction. The
+ * mmcra[slot] bits represent the slot number of a sampled instruction
+ * within an instruction group.  The slot will contain a value between 1
+ * and 5 if MMCRA_SAMPLE_ENABLE is set, otherwise 0.
  */
 static unsigned long get_pc(struct pt_regs *regs)
 {
        unsigned long pc = mfspr(SPRN_SIAR);
        unsigned long mmcra;
+       unsigned long slot;
 
        /* Cant do much about it */
        if (!cur_cpu_spec->oprofile_mmcra_sihv)
@@ -193,6 +201,12 @@ static unsigned long get_pc(struct pt_regs *regs)
 
        mmcra = mfspr(SPRN_MMCRA);
 
+       if (mmcra & MMCRA_SAMPLE_ENABLE) {
+               slot = ((mmcra & MMCRA_SLOT) >> MMCRA_SLOT_SHIFT);
+               if (slot > 1)
+                       pc += 4 * (slot - 1);
+       }
+
        /* Were we in the hypervisor? */
        if (firmware_has_feature(FW_FEATURE_LPAR) &&
            (mmcra & cur_cpu_spec->oprofile_mmcra_sihv))
diff --git a/include/asm-powerpc/reg.h b/include/asm-powerpc/reg.h
index 749c7f9..281011e 100644
--- a/include/asm-powerpc/reg.h
+++ b/include/asm-powerpc/reg.h
@@ -453,6 +453,8 @@
 #define SPRN_MMCRA     0x312
 #define   MMCRA_SIHV   0x10000000UL /* state of MSR HV when SIAR set */
 #define   MMCRA_SIPR   0x08000000UL /* state of MSR PR when SIAR set */
+#define   MMCRA_SLOT   0x07000000UL /* SLOT bits (37-39) */
+#define   MMCRA_SLOT_SHIFT     24
 #define   MMCRA_SAMPLE_ENABLE 0x00000001UL /* enable sampling */
 #define   POWER6_MMCRA_SIHV   0x0000040000000000ULL
 #define   POWER6_MMCRA_SIPR   0x0000020000000000ULL
-
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