Gitweb:     
http://git.kernel.org/git/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commit;h=39c7aa9ea9b6175f4313f69ef9f8e0a3a9bba5bb
Commit:     39c7aa9ea9b6175f4313f69ef9f8e0a3a9bba5bb
Parent:     680c45981ae2b4029878806d76aa17bb62d3c674
Author:     Magnus Damm <[EMAIL PROTECTED]>
AuthorDate: Fri Jul 20 12:10:29 2007 +0900
Committer:  Paul Mundt <[EMAIL PROTECTED]>
CommitDate: Fri Jul 20 12:18:21 2007 +0900

    sh: intc - add support for 7780
    
    This patch converts the cpu specific 7780 setup code to use the
    new intc controller. Many new vectors are added and also support for
    external interrupt sense configuration. So with this patch it is now
    possible to configure external interrupt pins as edge or level
    triggered using set_irq_type().
    
    No external interrupts are registered by default.
    Use plat_irq_setup_pins() to select between IRQ or IRL mode.
    
    This patch also fixes the Alarm IRQ for the RTC.
    
    Signed-off-by: Magnus Damm <[EMAIL PROTECTED]>
    Signed-off-by: Paul Mundt <[EMAIL PROTECTED]>
---
 arch/sh/Kconfig                        |    1 +
 arch/sh/configs/r7780mp_defconfig      |    2 +-
 arch/sh/configs/r7780rp_defconfig      |    2 +-
 arch/sh/configs/se7780_defconfig       |    1 +
 arch/sh/kernel/cpu/sh4a/setup-sh7780.c |  219 +++++++++++++++++++++++++++----
 arch/sh/mm/Kconfig                     |    2 +-
 include/asm-sh/hw_irq.h                |    3 +
 7 files changed, 198 insertions(+), 32 deletions(-)

diff --git a/arch/sh/Kconfig b/arch/sh/Kconfig
index 848a38b..2a9682e 100644
--- a/arch/sh/Kconfig
+++ b/arch/sh/Kconfig
@@ -253,6 +253,7 @@ config SH_7780_SOLUTION_ENGINE
        bool "SolutionEngine7780"
        select SOLUTION_ENGINE
        select SYS_SUPPORTS_PCI
+       select CPU_HAS_INTC2_IRQ
        depends on CPU_SUBTYPE_SH7780
        help
          Select 7780 SolutionEngine if configuring for a Renesas SH7780
diff --git a/arch/sh/configs/r7780mp_defconfig 
b/arch/sh/configs/r7780mp_defconfig
index 17f7402..ac4de49 100644
--- a/arch/sh/configs/r7780mp_defconfig
+++ b/arch/sh/configs/r7780mp_defconfig
@@ -191,7 +191,7 @@ CONFIG_SH_FPU=y
 CONFIG_SH_STORE_QUEUES=y
 CONFIG_SPECULATIVE_EXECUTION=y
 CONFIG_CPU_HAS_INTEVT=y
-CONFIG_CPU_HAS_INTC2_IRQ=y
+CONFIG_CPU_HAS_INTC_IRQ=y
 CONFIG_CPU_HAS_SR_RB=y
 
 #
diff --git a/arch/sh/configs/r7780rp_defconfig 
b/arch/sh/configs/r7780rp_defconfig
index 48c6a21..12cc019 100644
--- a/arch/sh/configs/r7780rp_defconfig
+++ b/arch/sh/configs/r7780rp_defconfig
@@ -241,7 +241,7 @@ CONFIG_SH_FPU=y
 CONFIG_SH_STORE_QUEUES=y
 CONFIG_SPECULATIVE_EXECUTION=y
 CONFIG_CPU_HAS_INTEVT=y
-CONFIG_CPU_HAS_INTC2_IRQ=y
+CONFIG_CPU_HAS_INTC_IRQ=y
 CONFIG_CPU_HAS_SR_RB=y
 
 #
diff --git a/arch/sh/configs/se7780_defconfig b/arch/sh/configs/se7780_defconfig
index 538661e..f68743d 100644
--- a/arch/sh/configs/se7780_defconfig
+++ b/arch/sh/configs/se7780_defconfig
@@ -218,6 +218,7 @@ CONFIG_SH_FPU=y
 # CONFIG_SH_STORE_QUEUES is not set
 CONFIG_CPU_HAS_INTEVT=y
 CONFIG_CPU_HAS_INTC2_IRQ=y
+CONFIG_CPU_HAS_INTC_IRQ=y
 CONFIG_CPU_HAS_SR_RB=y
 
 #
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7780.c 
b/arch/sh/kernel/cpu/sh4a/setup-sh7780.c
index 86cd628..a4127ec 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7780.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7780.c
@@ -30,7 +30,7 @@ static struct resource rtc_resources[] = {
        },
        [3] = {
                /* Alarm IRQ */
-               .start  = 23,
+               .start  = 20,
                .flags  = IORESOURCE_IRQ,
        },
 };
@@ -78,44 +78,205 @@ static int __init sh7780_devices_setup(void)
 }
 __initcall(sh7780_devices_setup);
 
-static struct intc2_data intc2_irq_table[] = {
-       { 28, 0, 24, 0, 0, 2 },         /* TMU0 */
+enum {
+       UNUSED = 0,
 
-       { 21, 1,  0, 0, 2, 2 },
-       { 22, 1,  1, 0, 2, 2 },
-       { 23, 1,  2, 0, 2, 2 },
+       /* interrupt sources */
 
-       { 40, 8, 24, 0, 3, 3 },         /* SCIF0 ERI */
-       { 41, 8, 24, 0, 3, 3 },         /* SCIF0 RXI */
-       { 42, 8, 24, 0, 3, 3 },         /* SCIF0 BRI */
-       { 43, 8, 24, 0, 3, 3 },         /* SCIF0 TXI */
+       IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH,
+       IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH,
+       IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH,
+       IRL_HHLL, IRL_HHLH, IRL_HHHL,
 
-       { 76, 8, 16, 0, 4, 3 },         /* SCIF1 ERI */
-       { 77, 8, 16, 0, 4, 3 },         /* SCIF1 RXI */
-       { 78, 8, 16, 0, 4, 3 },         /* SCIF1 BRI */
-       { 79, 8, 16, 0, 4, 3 },         /* SCIF1 TXI */
+       IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
+       RTC_ATI, RTC_PRI, RTC_CUI,
+       WDT,
+       TMU0, TMU1, TMU2, TMU2_TICPI,
+       HUDI,
+       DMAC0_DMINT0, DMAC0_DMINT1, DMAC0_DMINT2, DMAC0_DMINT3, DMAC0_DMAE,
+       SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI,
+       DMAC0_DMINT4, DMAC0_DMINT5, DMAC1_DMINT6, DMAC1_DMINT7,
+       CMT, HAC,
+       PCISERR, PCIINTA, PCIINTB, PCIINTC, PCIINTD,
+       PCIERR, PCIPWD3, PCIPWD2, PCIPWD1, PCIPWD0,
+       SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI,
+       SIOF, HSPI,
+       MMCIF_FSTAT, MMCIF_TRAN, MMCIF_ERR, MMCIF_FRDY,
+       DMAC1_DMINT8, DMAC1_DMINT9, DMAC1_DMINT10, DMAC1_DMINT11,
+       TMU3, TMU4, TMU5,
+       SSI,
+       FLCTL_FLSTE, FLCTL_FLEND, FLCTL_FLTRQ0, FLCTL_FLTRQ1,
+       GPIOI0, GPIOI1, GPIOI2, GPIOI3,
 
-       { 64, 0x10,  8, 0, 14, 2 },     /* PCIC0 */
-       { 65, 0x10,  0, 0, 15, 2 },     /* PCIC1 */
-       { 66, 0x14, 24, 0, 16, 2 },     /* PCIC2 */
-       { 67, 0x14, 16, 0, 17, 2 },     /* PCIC3 */
-       { 68, 0x14,  8, 0, 18, 2 },     /* PCIC4 */
+       /* interrupt groups */
+
+       RTC, TMU012, DMAC0, SCIF0, DMAC45, DMAC1,
+       PCIC5, SCIF1, MMCIF, TMU345, FLCTL, GPIO,
 };
 
-static struct intc2_desc intc2_irq_desc __read_mostly = {
-       .prio_base      = 0xffd40000,
-       .msk_base       = 0xffd40038,
-       .mskclr_base    = 0xffd4003c,
+static struct intc_vect vectors[] = {
+       INTC_VECT(RTC_ATI, 0x480), INTC_VECT(RTC_PRI, 0x4a0),
+       INTC_VECT(RTC_CUI, 0x4c0),
+       INTC_VECT(WDT, 0x560),
+       INTC_VECT(TMU0, 0x580), INTC_VECT(TMU1, 0x5a0),
+       INTC_VECT(TMU2, 0x5c0), INTC_VECT(TMU2_TICPI, 0x5e0),
+       INTC_VECT(HUDI, 0x600),
+       INTC_VECT(DMAC0_DMINT0, 0x640), INTC_VECT(DMAC0_DMINT1, 0x660),
+       INTC_VECT(DMAC0_DMINT2, 0x680), INTC_VECT(DMAC0_DMINT3, 0x6a0),
+       INTC_VECT(DMAC0_DMAE, 0x6c0),
+       INTC_VECT(SCIF0_ERI, 0x700), INTC_VECT(SCIF0_RXI, 0x720),
+       INTC_VECT(SCIF0_BRI, 0x740), INTC_VECT(SCIF0_TXI, 0x760),
+       INTC_VECT(DMAC0_DMINT4, 0x780), INTC_VECT(DMAC0_DMINT5, 0x7a0),
+       INTC_VECT(DMAC1_DMINT6, 0x7c0), INTC_VECT(DMAC1_DMINT7, 0x7e0),
+       INTC_VECT(CMT, 0x900), INTC_VECT(HAC, 0x980),
+       INTC_VECT(PCISERR, 0xa00), INTC_VECT(PCIINTA, 0xa20),
+       INTC_VECT(PCIINTB, 0xa40), INTC_VECT(PCIINTC, 0xa60),
+       INTC_VECT(PCIINTD, 0xa80), INTC_VECT(PCIERR, 0xaa0),
+       INTC_VECT(PCIPWD3, 0xac0), INTC_VECT(PCIPWD2, 0xae0),
+       INTC_VECT(PCIPWD1, 0xb00), INTC_VECT(PCIPWD0, 0xb20),
+       INTC_VECT(SCIF1_ERI, 0xb80), INTC_VECT(SCIF1_RXI, 0xba0),
+       INTC_VECT(SCIF1_BRI, 0xbc0), INTC_VECT(SCIF1_TXI, 0xbe0),
+       INTC_VECT(SIOF, 0xc00), INTC_VECT(HSPI, 0xc80),
+       INTC_VECT(MMCIF_FSTAT, 0xd00), INTC_VECT(MMCIF_TRAN, 0xd20),
+       INTC_VECT(MMCIF_ERR, 0xd40), INTC_VECT(MMCIF_FRDY, 0xd60),
+       INTC_VECT(DMAC1_DMINT8, 0xd80), INTC_VECT(DMAC1_DMINT9, 0xda0),
+       INTC_VECT(DMAC1_DMINT10, 0xdc0), INTC_VECT(DMAC1_DMINT11, 0xde0),
+       INTC_VECT(TMU3, 0xe00), INTC_VECT(TMU4, 0xe20),
+       INTC_VECT(TMU5, 0xe40),
+       INTC_VECT(SSI, 0xe80),
+       INTC_VECT(FLCTL_FLSTE, 0xf00), INTC_VECT(FLCTL_FLEND, 0xf20),
+       INTC_VECT(FLCTL_FLTRQ0, 0xf40), INTC_VECT(FLCTL_FLTRQ1, 0xf60),
+       INTC_VECT(GPIOI0, 0xf80), INTC_VECT(GPIOI1, 0xfa0),
+       INTC_VECT(GPIOI2, 0xfc0), INTC_VECT(GPIOI3, 0xfe0),
+};
 
-       .intc2_data     = intc2_irq_table,
-       .nr_irqs        = ARRAY_SIZE(intc2_irq_table),
+static struct intc_group groups[] = {
+       INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI),
+       INTC_GROUP(TMU012, TMU0, TMU1, TMU2, TMU2_TICPI),
+       INTC_GROUP(DMAC0, DMAC0_DMINT0, DMAC0_DMINT1, DMAC0_DMINT2,
+                  DMAC0_DMINT3, DMAC0_DMINT4, DMAC0_DMINT5, DMAC0_DMAE),
+       INTC_GROUP(SCIF0, SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI),
+       INTC_GROUP(DMAC1, DMAC1_DMINT6, DMAC1_DMINT7, DMAC1_DMINT8,
+                  DMAC1_DMINT9, DMAC1_DMINT10, DMAC1_DMINT11),
+       INTC_GROUP(PCIC5, PCIERR, PCIPWD3, PCIPWD2, PCIPWD1, PCIPWD0),
+       INTC_GROUP(SCIF1, SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI),
+       INTC_GROUP(MMCIF, MMCIF_FSTAT, MMCIF_TRAN, MMCIF_ERR, MMCIF_FRDY),
+       INTC_GROUP(TMU345, TMU3, TMU4, TMU5),
+       INTC_GROUP(FLCTL, FLCTL_FLSTE, FLCTL_FLEND,
+                  FLCTL_FLTRQ0, FLCTL_FLTRQ1),
+       INTC_GROUP(GPIO, GPIOI0, GPIOI1, GPIOI2, GPIOI3),
+};
 
-       .chip = {
-               .name   = "INTC2-sh7780",
-       },
+static struct intc_prio priorities[] = {
+       INTC_PRIO(SCIF0, 3),
+       INTC_PRIO(SCIF1, 3),
+};
+
+static struct intc_mask_reg mask_registers[] = {
+       { 0xffd40038, 0xffd4003c, 32, /* INT2MSKR / INT2MSKCR */
+         { 0, 0, 0, 0, 0, 0, GPIO, FLCTL,
+           SSI, MMCIF, HSPI, SIOF, PCIC5, PCIINTD, PCIINTC, PCIINTB,
+           PCIINTA, PCISERR, HAC, CMT, 0, 0, DMAC1, DMAC0,
+           HUDI, 0, WDT, SCIF1, SCIF0, RTC, TMU345, TMU012 } },
+};
+
+static struct intc_prio_reg prio_registers[] = {
+       { 0xffd40000, 32, 8, /* INT2PRI0 */ { TMU0, TMU1, TMU2, TMU2_TICPI } },
+       { 0xffd40004, 32, 8, /* INT2PRI1 */ { TMU3, TMU4, TMU5, RTC } },
+       { 0xffd40008, 32, 8, /* INT2PRI2 */ { SCIF0, SCIF1, WDT } },
+       { 0xffd4000c, 32, 8, /* INT2PRI3 */ { HUDI, DMAC0, DMAC1 } },
+       { 0xffd40010, 32, 8, /* INT2PRI4 */ { CMT, HAC, PCISERR, PCIINTA, } },
+       { 0xffd40014, 32, 8, /* INT2PRI5 */ { PCIINTB, PCIINTC,
+                                             PCIINTD, PCIC5 } },
+       { 0xffd40018, 32, 8, /* INT2PRI6 */ { SIOF, HSPI, MMCIF, SSI } },
+       { 0xffd4001c, 32, 8, /* INT2PRI7 */ { FLCTL, GPIO } },
+};
+
+static DECLARE_INTC_DESC(intc_desc, "sh7780", vectors, groups, priorities,
+                        mask_registers, prio_registers, NULL);
+
+/* Support for external interrupt pins in IRQ mode */
+
+static struct intc_vect irq_vectors[] = {
+       INTC_VECT(IRQ0, 0x240), INTC_VECT(IRQ1, 0x280),
+       INTC_VECT(IRQ2, 0x2c0), INTC_VECT(IRQ3, 0x300),
+       INTC_VECT(IRQ4, 0x340), INTC_VECT(IRQ5, 0x380),
+       INTC_VECT(IRQ6, 0x3c0), INTC_VECT(IRQ7, 0x200),
+};
+
+static struct intc_mask_reg irq_mask_registers[] = {
+       { 0xffd00044, 0xffd00064, 32, /* INTMSK0 / INTMSKCLR0 */
+         { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
+};
+
+static struct intc_prio_reg irq_prio_registers[] = {
+       { 0xffd00010, 32, 4, /* INTPRI */ { IRQ0, IRQ1, IRQ2, IRQ3,
+                                           IRQ4, IRQ5, IRQ6, IRQ7 } },
 };
 
+static struct intc_sense_reg irq_sense_registers[] = {
+       { 0xffd0001c, 32, 2, /* ICR1 */   { IRQ0, IRQ1, IRQ2, IRQ3,
+                                           IRQ4, IRQ5, IRQ6, IRQ7 } },
+};
+
+static DECLARE_INTC_DESC(intc_irq_desc, "sh7780-irq", irq_vectors,
+                        NULL, NULL, irq_mask_registers, irq_prio_registers,
+                        irq_sense_registers);
+
+/* External interrupt pins in IRL mode */
+
+static struct intc_vect irl_vectors[] = {
+       INTC_VECT(IRL_LLLL, 0x200), INTC_VECT(IRL_LLLH, 0x220),
+       INTC_VECT(IRL_LLHL, 0x240), INTC_VECT(IRL_LLHH, 0x260),
+       INTC_VECT(IRL_LHLL, 0x280), INTC_VECT(IRL_LHLH, 0x2a0),
+       INTC_VECT(IRL_LHHL, 0x2c0), INTC_VECT(IRL_LHHH, 0x2e0),
+       INTC_VECT(IRL_HLLL, 0x300), INTC_VECT(IRL_HLLH, 0x320),
+       INTC_VECT(IRL_HLHL, 0x340), INTC_VECT(IRL_HLHH, 0x360),
+       INTC_VECT(IRL_HHLL, 0x380), INTC_VECT(IRL_HHLH, 0x3a0),
+       INTC_VECT(IRL_HHHL, 0x3c0),
+};
+
+static struct intc_mask_reg irl3210_mask_registers[] = {
+       { 0xffd00080, 0xffd00084, 32, /* INTMSK2 / INTMSKCLR2 */
+         { IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH,
+           IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH,
+           IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH,
+           IRL_HHLL, IRL_HHLH, IRL_HHHL, } },
+};
+
+static struct intc_mask_reg irl7654_mask_registers[] = {
+       { 0xffd00080, 0xffd00084, 32, /* INTMSK2 / INTMSKCLR2 */
+         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+           IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH,
+           IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH,
+           IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH,
+           IRL_HHLL, IRL_HHLH, IRL_HHHL, } },
+};
+
+static DECLARE_INTC_DESC(intc_irl7654_desc, "sh7780-irl7654", irl_vectors,
+                        NULL, NULL, irl7654_mask_registers, NULL, NULL);
+
+static DECLARE_INTC_DESC(intc_irl3210_desc, "sh7780-irl3210", irl_vectors,
+                        NULL, NULL, irl3210_mask_registers, NULL, NULL);
+
 void __init plat_irq_setup(void)
 {
-       register_intc2_controller(&intc2_irq_desc);
+       register_intc_controller(&intc_desc);
+}
+
+void __init plat_irq_setup_pins(int mode)
+{
+       switch (mode) {
+       case IRQ_MODE_IRQ:
+               register_intc_controller(&intc_irq_desc);
+               break;
+       case IRQ_MODE_IRL7654:
+               register_intc_controller(&intc_irl7654_desc);
+               break;
+       case IRQ_MODE_IRL3210:
+               register_intc_controller(&intc_irl3210_desc);
+               break;
+       default:
+               BUG();
+       }
 }
diff --git a/arch/sh/mm/Kconfig b/arch/sh/mm/Kconfig
index 7c08729..697277a 100644
--- a/arch/sh/mm/Kconfig
+++ b/arch/sh/mm/Kconfig
@@ -189,7 +189,7 @@ config CPU_SUBTYPE_SH7770
 config CPU_SUBTYPE_SH7780
        bool "Support SH7780 processor"
        select CPU_SH4A
-       select CPU_HAS_INTC2_IRQ
+       select CPU_HAS_INTC_IRQ
 
 config CPU_SUBTYPE_SH7785
        bool "Support SH7785 processor"
diff --git a/include/asm-sh/hw_irq.h b/include/asm-sh/hw_irq.h
index 92c9efd..8c5e11b 100644
--- a/include/asm-sh/hw_irq.h
+++ b/include/asm-sh/hw_irq.h
@@ -115,4 +115,7 @@ void __init register_intc_controller(struct intc_desc 
*desc);
 
 void __init plat_irq_setup(void);
 
+enum { IRQ_MODE_IRQ, IRQ_MODE_IRL7654, IRQ_MODE_IRL3210 };
+void __init plat_irq_setup_pins(int mode);
+
 #endif /* __ASM_SH_HW_IRQ_H */
-
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