Gitweb:     
http://git.kernel.org/git/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commit;h=06cfa556949ead5d3c00dc68108c443be8dd8d17
Commit:     06cfa556949ead5d3c00dc68108c443be8dd8d17
Parent:     dd1313a167a9d29c349b3244dffac274bb0bf486
Author:     Ben Dooks <[EMAIL PROTECTED]>
AuthorDate: Sun Jul 22 16:23:02 2007 +0100
Committer:  Russell King <[EMAIL PROTECTED]>
CommitDate: Sun Jul 22 17:06:30 2007 +0100

    [ARM] 4524/1: S3C: Move register out of include/asm-arm/arch-s3c2410
    
    Move register and other definitions out of the
    include/asm-arm/arch-s3c2410 into the the arch
    directories of include/asm-arm/plat-s3c24xx and
    include/asm-arm/plat-s3c.
    
    This move is in preperation of the merging of
    s3c2400 and s3c6400.
    
    The following git mv commands are needed before
    this patch can be applied:
    
    git mv include/asm-arm/arch-s3c2410/regs-ac97.h 
include/asm-arm/plat-s3c/regs-ac97.h
    git mv include/asm-arm/arch-s3c2410/regs-adc.h 
include/asm-arm/plat-s3c/regs-adc.h
    git mv include/asm-arm/arch-s3c2410/regs-iis.h 
include/asm-arm/plat-s3c24xx/regs-iis.h
    git mv include/asm-arm/arch-s3c2410/regs-spi.h 
include/asm-arm/plat-s3c24xx/regs-spi.h
    git mv include/asm-arm/arch-s3c2410/regs-udc.h 
include/asm-arm/plat-s3c24xx/regs-udc.h
    git mv include/asm-arm/arch-s3c2410/udc.h include/asm-arm/plat-s3c24xx/udc.h
    
    Signed-off-by: Ben Dooks <[EMAIL PROTECTED]>
    Signed-off-by: Russell King <[EMAIL PROTECTED]>
---
 arch/arm/mach-s3c2410/dma.c              |    6 +-
 arch/arm/mach-s3c2410/mach-h1940.c       |    2 +-
 arch/arm/mach-s3c2410/mach-qt2410.c      |    2 +-
 arch/arm/mach-s3c2412/dma.c              |    6 +-
 arch/arm/mach-s3c2412/mach-smdk2413.c    |    2 +-
 arch/arm/mach-s3c2412/s3c2412.c          |    2 +-
 arch/arm/mach-s3c2440/dma.c              |    6 +-
 arch/arm/mach-s3c2443/dma.c              |    6 +-
 arch/arm/plat-s3c24xx/devs.c             |    4 +-
 include/asm-arm/arch-s3c2410/regs-ac97.h |   67 -------------
 include/asm-arm/arch-s3c2410/regs-adc.h  |   60 ------------
 include/asm-arm/arch-s3c2410/regs-iis.h  |   77 ---------------
 include/asm-arm/arch-s3c2410/regs-spi.h  |   54 -----------
 include/asm-arm/arch-s3c2410/regs-udc.h  |  153 ------------------------------
 include/asm-arm/arch-s3c2410/udc.h       |   36 -------
 include/asm-arm/plat-s3c/regs-ac97.h     |   67 +++++++++++++
 include/asm-arm/plat-s3c/regs-adc.h      |   60 ++++++++++++
 include/asm-arm/plat-s3c24xx/regs-iis.h  |   77 +++++++++++++++
 include/asm-arm/plat-s3c24xx/regs-spi.h  |   54 +++++++++++
 include/asm-arm/plat-s3c24xx/regs-udc.h  |  153 ++++++++++++++++++++++++++++++
 include/asm-arm/plat-s3c24xx/udc.h       |   36 +++++++
 21 files changed, 465 insertions(+), 465 deletions(-)

diff --git a/arch/arm/mach-s3c2410/dma.c b/arch/arm/mach-s3c2410/dma.c
index 5620ca4..80d8373 100644
--- a/arch/arm/mach-s3c2410/dma.c
+++ b/arch/arm/mach-s3c2410/dma.c
@@ -25,12 +25,12 @@
 
 #include <asm/plat-s3c/regs-serial.h>
 #include <asm/arch/regs-gpio.h>
-#include <asm/arch/regs-ac97.h>
+#include <asm/plat-s3c/regs-ac97.h>
 #include <asm/arch/regs-mem.h>
 #include <asm/arch/regs-lcd.h>
 #include <asm/arch/regs-sdi.h>
-#include <asm/arch/regs-iis.h>
-#include <asm/arch/regs-spi.h>
+#include <asm/plat-s3c24xx/regs-iis.h>
+#include <asm/plat-s3c24xx/regs-spi.h>
 
 static struct s3c24xx_dma_map __initdata s3c2410_dma_mappings[] = {
        [DMACH_XD0] = {
diff --git a/arch/arm/mach-s3c2410/mach-h1940.c 
b/arch/arm/mach-s3c2410/mach-h1940.c
index 4102235..9a172b4 100644
--- a/arch/arm/mach-s3c2410/mach-h1940.c
+++ b/arch/arm/mach-s3c2410/mach-h1940.c
@@ -38,7 +38,7 @@
 #include <asm/arch/h1940.h>
 #include <asm/arch/h1940-latch.h>
 #include <asm/arch/fb.h>
-#include <asm/arch/udc.h>
+#include <asm/plat-s3c24xx/udc.h>
 
 #include <asm/plat-s3c24xx/clock.h>
 #include <asm/plat-s3c24xx/devs.h>
diff --git a/arch/arm/mach-s3c2410/mach-qt2410.c 
b/arch/arm/mach-s3c2410/mach-qt2410.c
index 6cb4a0d..e670b1e 100644
--- a/arch/arm/mach-s3c2410/mach-qt2410.c
+++ b/arch/arm/mach-s3c2410/mach-qt2410.c
@@ -52,7 +52,7 @@
 #include <asm/plat-s3c/regs-serial.h>
 #include <asm/arch/fb.h>
 #include <asm/plat-s3c/nand.h>
-#include <asm/arch/udc.h>
+#include <asm/plat-s3c24xx/udc.h>
 #include <asm/arch/spi.h>
 #include <asm/arch/spi-gpio.h>
 
diff --git a/arch/arm/mach-s3c2412/dma.c b/arch/arm/mach-s3c2412/dma.c
index 48413df..4b9425c 100644
--- a/arch/arm/mach-s3c2412/dma.c
+++ b/arch/arm/mach-s3c2412/dma.c
@@ -26,12 +26,12 @@
 
 #include <asm/plat-s3c/regs-serial.h>
 #include <asm/arch/regs-gpio.h>
-#include <asm/arch/regs-ac97.h>
+#include <asm/plat-s3c/regs-ac97.h>
 #include <asm/arch/regs-mem.h>
 #include <asm/arch/regs-lcd.h>
 #include <asm/arch/regs-sdi.h>
-#include <asm/arch/regs-iis.h>
-#include <asm/arch/regs-spi.h>
+#include <asm/plat-s3c24xx/regs-iis.h>
+#include <asm/plat-s3c24xx/regs-spi.h>
 
 #define MAP(x) { (x)| DMA_CH_VALID, (x)| DMA_CH_VALID, (x)| DMA_CH_VALID, (x)| 
DMA_CH_VALID }
 
diff --git a/arch/arm/mach-s3c2412/mach-smdk2413.c 
b/arch/arm/mach-s3c2412/mach-smdk2413.c
index bbc609c..b126a53 100644
--- a/arch/arm/mach-s3c2412/mach-smdk2413.c
+++ b/arch/arm/mach-s3c2412/mach-smdk2413.c
@@ -37,7 +37,7 @@
 #include <asm/arch/regs-lcd.h>
 
 #include <asm/arch/idle.h>
-#include <asm/arch/udc.h>
+#include <asm/plat-s3c24xx/udc.h>
 #include <asm/arch/fb.h>
 
 #include <asm/plat-s3c24xx/s3c2410.h>
diff --git a/arch/arm/mach-s3c2412/s3c2412.c b/arch/arm/mach-s3c2412/s3c2412.c
index 66f471a..e0ccb40 100644
--- a/arch/arm/mach-s3c2412/s3c2412.c
+++ b/arch/arm/mach-s3c2412/s3c2412.c
@@ -39,7 +39,7 @@
 #include <asm/arch/regs-gpio.h>
 #include <asm/arch/regs-gpioj.h>
 #include <asm/arch/regs-dsc.h>
-#include <asm/arch/regs-spi.h>
+#include <asm/plat-s3c24xx/regs-spi.h>
 #include <asm/arch/regs-s3c2412.h>
 
 #include <asm/plat-s3c24xx/s3c2412.h>
diff --git a/arch/arm/mach-s3c2440/dma.c b/arch/arm/mach-s3c2440/dma.c
index 13e4be3..f509f06 100644
--- a/arch/arm/mach-s3c2440/dma.c
+++ b/arch/arm/mach-s3c2440/dma.c
@@ -25,12 +25,12 @@
 
 #include <asm/plat-s3c/regs-serial.h>
 #include <asm/arch/regs-gpio.h>
-#include <asm/arch/regs-ac97.h>
+#include <asm/plat-s3c/regs-ac97.h>
 #include <asm/arch/regs-mem.h>
 #include <asm/arch/regs-lcd.h>
 #include <asm/arch/regs-sdi.h>
-#include <asm/arch/regs-iis.h>
-#include <asm/arch/regs-spi.h>
+#include <asm/plat-s3c24xx/regs-iis.h>
+#include <asm/plat-s3c24xx/regs-spi.h>
 
 static struct s3c24xx_dma_map __initdata s3c2440_dma_mappings[] = {
        [DMACH_XD0] = {
diff --git a/arch/arm/mach-s3c2443/dma.c b/arch/arm/mach-s3c2443/dma.c
index d8bb434..fc3ede8 100644
--- a/arch/arm/mach-s3c2443/dma.c
+++ b/arch/arm/mach-s3c2443/dma.c
@@ -26,12 +26,12 @@
 
 #include <asm/plat-s3c/regs-serial.h>
 #include <asm/arch/regs-gpio.h>
-#include <asm/arch/regs-ac97.h>
+#include <asm/plat-s3c/regs-ac97.h>
 #include <asm/arch/regs-mem.h>
 #include <asm/arch/regs-lcd.h>
 #include <asm/arch/regs-sdi.h>
-#include <asm/arch/regs-iis.h>
-#include <asm/arch/regs-spi.h>
+#include <asm/plat-s3c24xx/regs-iis.h>
+#include <asm/plat-s3c24xx/regs-spi.h>
 
 #define MAP(x) { \
                [0]     = (x) | DMA_CH_VALID,   \
diff --git a/arch/arm/plat-s3c24xx/devs.c b/arch/arm/plat-s3c24xx/devs.c
index 9941508..e546e93 100644
--- a/arch/arm/plat-s3c24xx/devs.c
+++ b/arch/arm/plat-s3c24xx/devs.c
@@ -29,11 +29,11 @@
 #include <asm/irq.h>
 
 #include <asm/plat-s3c/regs-serial.h>
-#include <asm/arch/udc.h>
+#include <asm/plat-s3c24xx/udc.h>
 
 #include <asm/plat-s3c24xx/devs.h>
 #include <asm/plat-s3c24xx/cpu.h>
-#include <asm/arch/regs-spi.h>
+#include <asm/plat-s3c24xx/regs-spi.h>
 
 /* Serial port registrations */
 
diff --git a/include/asm-arm/arch-s3c2410/regs-ac97.h 
b/include/asm-arm/arch-s3c2410/regs-ac97.h
deleted file mode 100644
index b004dee..0000000
--- a/include/asm-arm/arch-s3c2410/regs-ac97.h
+++ /dev/null
@@ -1,67 +0,0 @@
-/* linux/include/asm-arm/arch-s3c2410/regs-ac97.h
- *
- * Copyright (c) 2006 Simtec Electronics <[EMAIL PROTECTED]>
- *             http://www.simtec.co.uk/products/SWLINUX/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * S3C2440 AC97 Controller
-*/
-
-#ifndef __ASM_ARCH_REGS_AC97_H
-#define __ASM_ARCH_REGS_AC97_H __FILE__
-
-#define S3C_AC97_GLBCTRL                               (0x00)
-
-#define S3C_AC97_GLBCTRL_CODECREADYIE                  (1<<22)
-#define S3C_AC97_GLBCTRL_PCMOUTURIE                    (1<<21)
-#define S3C_AC97_GLBCTRL_PCMINORIE                     (1<<20)
-#define S3C_AC97_GLBCTRL_MICINORIE                     (1<<19)
-#define S3C_AC97_GLBCTRL_PCMOUTTIE                     (1<<18)
-#define S3C_AC97_GLBCTRL_PCMINTIE                      (1<<17)
-#define S3C_AC97_GLBCTRL_MICINTIE                      (1<<16)
-#define S3C_AC97_GLBCTRL_PCMOUTTM_OFF                  (0<<12)
-#define S3C_AC97_GLBCTRL_PCMOUTTM_PIO                  (1<<12)
-#define S3C_AC97_GLBCTRL_PCMOUTTM_DMA                  (2<<12)
-#define S3C_AC97_GLBCTRL_PCMOUTTM_MASK                 (3<<12)
-#define S3C_AC97_GLBCTRL_PCMINTM_OFF                   (0<<10)
-#define S3C_AC97_GLBCTRL_PCMINTM_PIO                   (1<<10)
-#define S3C_AC97_GLBCTRL_PCMINTM_DMA                   (2<<10)
-#define S3C_AC97_GLBCTRL_PCMINTM_MASK                  (3<<10)
-#define S3C_AC97_GLBCTRL_MICINTM_OFF                   (0<<8)
-#define S3C_AC97_GLBCTRL_MICINTM_PIO                   (1<<8)
-#define S3C_AC97_GLBCTRL_MICINTM_DMA                   (2<<8)
-#define S3C_AC97_GLBCTRL_MICINTM_MASK                  (3<<8)
-#define S3C_AC97_GLBCTRL_TRANSFERDATAENABLE            (1<<3)
-#define S3C_AC97_GLBCTRL_ACLINKON                      (1<<2)
-#define S3C_AC97_GLBCTRL_WARMRESET                     (1<<1)
-#define S3C_AC97_GLBCTRL_COLDRESET                     (1<<0)
-
-#define S3C_AC97_GLBSTAT                               (0x04)
-
-#define S3C_AC97_GLBSTAT_CODECREADY                    (1<<22)
-#define S3C_AC97_GLBSTAT_PCMOUTUR                      (1<<21)
-#define S3C_AC97_GLBSTAT_PCMINORI                      (1<<20)
-#define S3C_AC97_GLBSTAT_MICINORI                      (1<<19)
-#define S3C_AC97_GLBSTAT_PCMOUTTI                      (1<<18)
-#define S3C_AC97_GLBSTAT_PCMINTI                       (1<<17)
-#define S3C_AC97_GLBSTAT_MICINTI                       (1<<16)
-#define S3C_AC97_GLBSTAT_MAINSTATE_IDLE                        (0<<0)
-#define S3C_AC97_GLBSTAT_MAINSTATE_INIT                        (1<<0)
-#define S3C_AC97_GLBSTAT_MAINSTATE_READY               (2<<0)
-#define S3C_AC97_GLBSTAT_MAINSTATE_ACTIVE              (3<<0)
-#define S3C_AC97_GLBSTAT_MAINSTATE_LP                  (4<<0)
-#define S3C_AC97_GLBSTAT_MAINSTATE_WARM                        (5<<0)
-
-#define S3C_AC97_CODEC_CMD                             (0x08)
-
-#define S3C_AC97_CODEC_CMD_READ                                (1<<23)
-
-#define S3C_AC97_STAT                                  (0x0c)
-#define S3C_AC97_PCM_ADDR                              (0x10)
-#define S3C_AC97_PCM_DATA                              (0x18)
-#define S3C_AC97_MIC_DATA                              (0x1C)
-
-#endif /* __ASM_ARCH_REGS_AC97_H */
diff --git a/include/asm-arm/arch-s3c2410/regs-adc.h 
b/include/asm-arm/arch-s3c2410/regs-adc.h
deleted file mode 100644
index c7f2319..0000000
--- a/include/asm-arm/arch-s3c2410/regs-adc.h
+++ /dev/null
@@ -1,60 +0,0 @@
-/* linux/include/asm-arm/arch-s3c2410/regs-adc.h
- *
- * Copyright (c) 2004 Shannon Holland <[EMAIL PROTECTED]>
- *
- * This program is free software; yosu can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * S3C2410 ADC registers
-*/
-
-#ifndef __ASM_ARCH_REGS_ADC_H
-#define __ASM_ARCH_REGS_ADC_H "regs-adc.h"
-
-#define S3C2410_ADCREG(x) (x)
-
-#define S3C2410_ADCCON    S3C2410_ADCREG(0x00)
-#define S3C2410_ADCTSC    S3C2410_ADCREG(0x04)
-#define S3C2410_ADCDLY    S3C2410_ADCREG(0x08)
-#define S3C2410_ADCDAT0           S3C2410_ADCREG(0x0C)
-#define S3C2410_ADCDAT1           S3C2410_ADCREG(0x10)
-
-
-/* ADCCON Register Bits */
-#define S3C2410_ADCCON_ECFLG           (1<<15)
-#define S3C2410_ADCCON_PRSCEN          (1<<14)
-#define S3C2410_ADCCON_PRSCVL(x)       (((x)&0xFF)<<6)
-#define S3C2410_ADCCON_PRSCVLMASK      (0xFF<<6)
-#define S3C2410_ADCCON_SELMUX(x)       (((x)&0x7)<<3)
-#define S3C2410_ADCCON_MUXMASK         (0x7<<3)
-#define S3C2410_ADCCON_STDBM           (1<<2)
-#define S3C2410_ADCCON_READ_START      (1<<1)
-#define S3C2410_ADCCON_ENABLE_START    (1<<0)
-#define S3C2410_ADCCON_STARTMASK       (0x3<<0)
-
-
-/* ADCTSC Register Bits */
-#define S3C2410_ADCTSC_YM_SEN          (1<<7)
-#define S3C2410_ADCTSC_YP_SEN          (1<<6)
-#define S3C2410_ADCTSC_XM_SEN          (1<<5)
-#define S3C2410_ADCTSC_XP_SEN          (1<<4)
-#define S3C2410_ADCTSC_PULL_UP_DISABLE (1<<3)
-#define S3C2410_ADCTSC_AUTO_PST                (1<<2)
-#define S3C2410_ADCTSC_XY_PST(x)       (((x)&0x3)<<0)
-
-/* ADCDAT0 Bits */
-#define S3C2410_ADCDAT0_UPDOWN         (1<<15)
-#define S3C2410_ADCDAT0_AUTO_PST       (1<<14)
-#define S3C2410_ADCDAT0_XY_PST         (0x3<<12)
-#define S3C2410_ADCDAT0_XPDATA_MASK    (0x03FF)
-
-/* ADCDAT1 Bits */
-#define S3C2410_ADCDAT1_UPDOWN         (1<<15)
-#define S3C2410_ADCDAT1_AUTO_PST       (1<<14)
-#define S3C2410_ADCDAT1_XY_PST         (0x3<<12)
-#define S3C2410_ADCDAT1_YPDATA_MASK    (0x03FF)
-
-#endif /* __ASM_ARCH_REGS_ADC_H */
-
-
diff --git a/include/asm-arm/arch-s3c2410/regs-iis.h 
b/include/asm-arm/arch-s3c2410/regs-iis.h
deleted file mode 100644
index eaf7791..0000000
--- a/include/asm-arm/arch-s3c2410/regs-iis.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/* linux/include/asm-arm/arch-s3c2410/regs-iis.h
- *
- * Copyright (c) 2003 Simtec Electronics <[EMAIL PROTECTED]>
- *                   http://www.simtec.co.uk/products/SWLINUX/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * S3C2410 IIS register definition
-*/
-
-#ifndef __ASM_ARCH_REGS_IIS_H
-#define __ASM_ARCH_REGS_IIS_H
-
-#define S3C2410_IISCON  (0x00)
-
-#define S3C2410_IISCON_LRINDEX   (1<<8)
-#define S3C2410_IISCON_TXFIFORDY  (1<<7)
-#define S3C2410_IISCON_RXFIFORDY  (1<<6)
-#define S3C2410_IISCON_TXDMAEN   (1<<5)
-#define S3C2410_IISCON_RXDMAEN   (1<<4)
-#define S3C2410_IISCON_TXIDLE    (1<<3)
-#define S3C2410_IISCON_RXIDLE    (1<<2)
-#define S3C2410_IISCON_PSCEN     (1<<1)
-#define S3C2410_IISCON_IISEN     (1<<0)
-
-#define S3C2410_IISMOD  (0x04)
-
-#define S3C2440_IISMOD_MPLL      (1<<9)
-#define S3C2410_IISMOD_SLAVE     (1<<8)
-#define S3C2410_IISMOD_NOXFER    (0<<6)
-#define S3C2410_IISMOD_RXMODE    (1<<6)
-#define S3C2410_IISMOD_TXMODE    (2<<6)
-#define S3C2410_IISMOD_TXRXMODE          (3<<6)
-#define S3C2410_IISMOD_LR_LLOW   (0<<5)
-#define S3C2410_IISMOD_LR_RLOW   (1<<5)
-#define S3C2410_IISMOD_IIS       (0<<4)
-#define S3C2410_IISMOD_MSB       (1<<4)
-#define S3C2410_IISMOD_8BIT      (0<<3)
-#define S3C2410_IISMOD_16BIT     (1<<3)
-#define S3C2410_IISMOD_BITMASK   (1<<3)
-#define S3C2410_IISMOD_256FS     (0<<2)
-#define S3C2410_IISMOD_384FS     (1<<2)
-#define S3C2410_IISMOD_16FS      (0<<0)
-#define S3C2410_IISMOD_32FS      (1<<0)
-#define S3C2410_IISMOD_48FS      (2<<0)
-#define S3C2410_IISMOD_FS_MASK   (3<<0)
-
-#define S3C2410_IISPSR         (0x08)
-#define S3C2410_IISPSR_INTMASK (31<<5)
-#define S3C2410_IISPSR_INTSHIFT        (5)
-#define S3C2410_IISPSR_EXTMASK (31<<0)
-#define S3C2410_IISPSR_EXTSHFIT        (0)
-
-#define S3C2410_IISFCON  (0x0c)
-
-#define S3C2410_IISFCON_TXDMA    (1<<15)
-#define S3C2410_IISFCON_RXDMA    (1<<14)
-#define S3C2410_IISFCON_TXENABLE  (1<<13)
-#define S3C2410_IISFCON_RXENABLE  (1<<12)
-#define S3C2410_IISFCON_TXMASK   (0x3f << 6)
-#define S3C2410_IISFCON_TXSHIFT          (6)
-#define S3C2410_IISFCON_RXMASK   (0x3f)
-#define S3C2410_IISFCON_RXSHIFT          (0)
-
-#define S3C2400_IISFCON_TXDMA     (1<<11)
-#define S3C2400_IISFCON_RXDMA     (1<<10)
-#define S3C2400_IISFCON_TXENABLE  (1<<9)
-#define S3C2400_IISFCON_RXENABLE  (1<<8)
-#define S3C2400_IISFCON_TXMASK   (0x07 << 4)
-#define S3C2400_IISFCON_TXSHIFT          (4)
-#define S3C2400_IISFCON_RXMASK   (0x07)
-#define S3C2400_IISFCON_RXSHIFT          (0)
-
-#define S3C2410_IISFIFO  (0x10)
-#endif /* __ASM_ARCH_REGS_IIS_H */
diff --git a/include/asm-arm/arch-s3c2410/regs-spi.h 
b/include/asm-arm/arch-s3c2410/regs-spi.h
deleted file mode 100644
index 4a499a1..0000000
--- a/include/asm-arm/arch-s3c2410/regs-spi.h
+++ /dev/null
@@ -1,54 +0,0 @@
-/* linux/include/asm-arm/arch-s3c2410/regs-spi.h
- *
- * Copyright (c) 2004 Fetron GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * S3C2410 SPI register definition
-*/
-
-#ifndef __ASM_ARCH_REGS_SPI_H
-#define __ASM_ARCH_REGS_SPI_H
-
-#define S3C2410_SPI1   (0x20)
-#define S3C2412_SPI1   (0x100)
-
-#define S3C2410_SPCON  (0x00)
-
-#define S3C2410_SPCON_SMOD_DMA   (2<<5)        /* DMA mode */
-#define S3C2410_SPCON_SMOD_INT   (1<<5)        /* interrupt mode */
-#define S3C2410_SPCON_SMOD_POLL   (0<<5)       /* polling mode */
-#define S3C2410_SPCON_ENSCK      (1<<4)        /* Enable SCK */
-#define S3C2410_SPCON_MSTR       (1<<3)        /* Master/Slave select
-                                                  0: slave, 1: master */
-#define S3C2410_SPCON_CPOL_HIGH          (1<<2)        /* Clock polarity 
select */
-#define S3C2410_SPCON_CPOL_LOW   (0<<2)        /* Clock polarity select */
-
-#define S3C2410_SPCON_CPHA_FMTB          (1<<1)        /* Clock Phase Select */
-#define S3C2410_SPCON_CPHA_FMTA          (0<<1)        /* Clock Phase Select */
-
-#define S3C2410_SPCON_TAGD       (1<<0)        /* Tx auto garbage data mode */
-
-
-#define S3C2410_SPSTA   (0x04)
-
-#define S3C2410_SPSTA_DCOL       (1<<2)        /* Data Collision Error */
-#define S3C2410_SPSTA_MULD       (1<<1)        /* Multi Master Error */
-#define S3C2410_SPSTA_READY      (1<<0)        /* Data Tx/Rx ready */
-
-
-#define S3C2410_SPPIN   (0x08)
-
-#define S3C2410_SPPIN_ENMUL      (1<<2)        /* Multi Master Error detect */
-#define S3C2410_SPPIN_RESERVED   (1<<1)
-#define S3C2400_SPPIN_nCS        (1<<1)        /* SPI Card Select */
-#define S3C2410_SPPIN_KEEP       (1<<0)        /* Master Out keep */
-
-
-#define S3C2410_SPPRE   (0x0C)
-#define S3C2410_SPTDAT  (0x10)
-#define S3C2410_SPRDAT  (0x14)
-
-#endif /* __ASM_ARCH_REGS_SPI_H */
diff --git a/include/asm-arm/arch-s3c2410/regs-udc.h 
b/include/asm-arm/arch-s3c2410/regs-udc.h
deleted file mode 100644
index e1e9805..0000000
--- a/include/asm-arm/arch-s3c2410/regs-udc.h
+++ /dev/null
@@ -1,153 +0,0 @@
-/* linux/include/asm-arm/arch-s3c2410/regs-udc.h
- *
- * Copyright (C) 2004 Herbert Poetzl <[EMAIL PROTECTED]>
- *
- * This include file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
-*/
-
-#ifndef __ASM_ARCH_REGS_UDC_H
-#define __ASM_ARCH_REGS_UDC_H
-
-#define S3C2410_USBDREG(x) (x)
-
-#define S3C2410_UDC_FUNC_ADDR_REG      S3C2410_USBDREG(0x0140)
-#define S3C2410_UDC_PWR_REG            S3C2410_USBDREG(0x0144)
-#define S3C2410_UDC_EP_INT_REG         S3C2410_USBDREG(0x0148)
-
-#define S3C2410_UDC_USB_INT_REG                S3C2410_USBDREG(0x0158)
-#define S3C2410_UDC_EP_INT_EN_REG      S3C2410_USBDREG(0x015c)
-
-#define S3C2410_UDC_USB_INT_EN_REG     S3C2410_USBDREG(0x016c)
-
-#define S3C2410_UDC_FRAME_NUM1_REG     S3C2410_USBDREG(0x0170)
-#define S3C2410_UDC_FRAME_NUM2_REG     S3C2410_USBDREG(0x0174)
-
-#define S3C2410_UDC_EP0_FIFO_REG       S3C2410_USBDREG(0x01c0)
-#define S3C2410_UDC_EP1_FIFO_REG       S3C2410_USBDREG(0x01c4)
-#define S3C2410_UDC_EP2_FIFO_REG       S3C2410_USBDREG(0x01c8)
-#define S3C2410_UDC_EP3_FIFO_REG       S3C2410_USBDREG(0x01cc)
-#define S3C2410_UDC_EP4_FIFO_REG       S3C2410_USBDREG(0x01d0)
-
-#define S3C2410_UDC_EP1_DMA_CON                S3C2410_USBDREG(0x0200)
-#define S3C2410_UDC_EP1_DMA_UNIT       S3C2410_USBDREG(0x0204)
-#define S3C2410_UDC_EP1_DMA_FIFO       S3C2410_USBDREG(0x0208)
-#define S3C2410_UDC_EP1_DMA_TTC_L      S3C2410_USBDREG(0x020c)
-#define S3C2410_UDC_EP1_DMA_TTC_M      S3C2410_USBDREG(0x0210)
-#define S3C2410_UDC_EP1_DMA_TTC_H      S3C2410_USBDREG(0x0214)
-
-#define S3C2410_UDC_EP2_DMA_CON                S3C2410_USBDREG(0x0218)
-#define S3C2410_UDC_EP2_DMA_UNIT       S3C2410_USBDREG(0x021c)
-#define S3C2410_UDC_EP2_DMA_FIFO       S3C2410_USBDREG(0x0220)
-#define S3C2410_UDC_EP2_DMA_TTC_L      S3C2410_USBDREG(0x0224)
-#define S3C2410_UDC_EP2_DMA_TTC_M      S3C2410_USBDREG(0x0228)
-#define S3C2410_UDC_EP2_DMA_TTC_H      S3C2410_USBDREG(0x022c)
-
-#define S3C2410_UDC_EP3_DMA_CON                S3C2410_USBDREG(0x0240)
-#define S3C2410_UDC_EP3_DMA_UNIT       S3C2410_USBDREG(0x0244)
-#define S3C2410_UDC_EP3_DMA_FIFO       S3C2410_USBDREG(0x0248)
-#define S3C2410_UDC_EP3_DMA_TTC_L      S3C2410_USBDREG(0x024c)
-#define S3C2410_UDC_EP3_DMA_TTC_M      S3C2410_USBDREG(0x0250)
-#define S3C2410_UDC_EP3_DMA_TTC_H      S3C2410_USBDREG(0x0254)
-
-#define S3C2410_UDC_EP4_DMA_CON                S3C2410_USBDREG(0x0258)
-#define S3C2410_UDC_EP4_DMA_UNIT       S3C2410_USBDREG(0x025c)
-#define S3C2410_UDC_EP4_DMA_FIFO       S3C2410_USBDREG(0x0260)
-#define S3C2410_UDC_EP4_DMA_TTC_L      S3C2410_USBDREG(0x0264)
-#define S3C2410_UDC_EP4_DMA_TTC_M      S3C2410_USBDREG(0x0268)
-#define S3C2410_UDC_EP4_DMA_TTC_H      S3C2410_USBDREG(0x026c)
-
-#define S3C2410_UDC_INDEX_REG          S3C2410_USBDREG(0x0178)
-
-/* indexed registers */
-
-#define S3C2410_UDC_MAXP_REG           S3C2410_USBDREG(0x0180)
-
-#define S3C2410_UDC_EP0_CSR_REG                S3C2410_USBDREG(0x0184)
-
-#define S3C2410_UDC_IN_CSR1_REG                S3C2410_USBDREG(0x0184)
-#define S3C2410_UDC_IN_CSR2_REG                S3C2410_USBDREG(0x0188)
-
-#define S3C2410_UDC_OUT_CSR1_REG       S3C2410_USBDREG(0x0190)
-#define S3C2410_UDC_OUT_CSR2_REG       S3C2410_USBDREG(0x0194)
-#define S3C2410_UDC_OUT_FIFO_CNT1_REG  S3C2410_USBDREG(0x0198)
-#define S3C2410_UDC_OUT_FIFO_CNT2_REG  S3C2410_USBDREG(0x019c)
-
-#define S3C2410_UDC_FUNCADDR_UPDATE    (1<<7)
-
-#define S3C2410_UDC_PWR_ISOUP          (1<<7) // R/W
-#define S3C2410_UDC_PWR_RESET          (1<<3) // R
-#define S3C2410_UDC_PWR_RESUME         (1<<2) // R/W
-#define S3C2410_UDC_PWR_SUSPEND                (1<<1) // R
-#define S3C2410_UDC_PWR_ENSUSPEND      (1<<0) // R/W
-
-#define S3C2410_UDC_PWR_DEFAULT                0x00
-
-#define S3C2410_UDC_INT_EP4            (1<<4) // R/W (clear only)
-#define S3C2410_UDC_INT_EP3            (1<<3) // R/W (clear only)
-#define S3C2410_UDC_INT_EP2            (1<<2) // R/W (clear only)
-#define S3C2410_UDC_INT_EP1            (1<<1) // R/W (clear only)
-#define S3C2410_UDC_INT_EP0            (1<<0) // R/W (clear only)
-
-#define S3C2410_UDC_USBINT_RESET       (1<<2) // R/W (clear only)
-#define S3C2410_UDC_USBINT_RESUME      (1<<1) // R/W (clear only)
-#define S3C2410_UDC_USBINT_SUSPEND     (1<<0) // R/W (clear only)
-
-#define S3C2410_UDC_INTE_EP4           (1<<4) // R/W
-#define S3C2410_UDC_INTE_EP3           (1<<3) // R/W
-#define S3C2410_UDC_INTE_EP2           (1<<2) // R/W
-#define S3C2410_UDC_INTE_EP1           (1<<1) // R/W
-#define S3C2410_UDC_INTE_EP0           (1<<0) // R/W
-
-#define S3C2410_UDC_USBINTE_RESET      (1<<2) // R/W
-#define S3C2410_UDC_USBINTE_SUSPEND    (1<<0) // R/W
-
-
-#define S3C2410_UDC_INDEX_EP0          (0x00)
-#define S3C2410_UDC_INDEX_EP1          (0x01) // ??
-#define S3C2410_UDC_INDEX_EP2          (0x02) // ??
-#define S3C2410_UDC_INDEX_EP3          (0x03) // ??
-#define S3C2410_UDC_INDEX_EP4          (0x04) // ??
-
-#define S3C2410_UDC_ICSR1_CLRDT                (1<<6) // R/W
-#define S3C2410_UDC_ICSR1_SENTSTL      (1<<5) // R/W (clear only)
-#define S3C2410_UDC_ICSR1_SENDSTL      (1<<4) // R/W
-#define S3C2410_UDC_ICSR1_FFLUSH       (1<<3) // W   (set only)
-#define S3C2410_UDC_ICSR1_UNDRUN       (1<<2) // R/W (clear only)
-#define S3C2410_UDC_ICSR1_PKTRDY       (1<<0) // R/W (set only)
-
-#define S3C2410_UDC_ICSR2_AUTOSET      (1<<7) // R/W
-#define S3C2410_UDC_ICSR2_ISO          (1<<6) // R/W
-#define S3C2410_UDC_ICSR2_MODEIN       (1<<5) // R/W
-#define S3C2410_UDC_ICSR2_DMAIEN       (1<<4) // R/W
-
-#define S3C2410_UDC_OCSR1_CLRDT                (1<<7) // R/W
-#define S3C2410_UDC_OCSR1_SENTSTL      (1<<6) // R/W (clear only)
-#define S3C2410_UDC_OCSR1_SENDSTL      (1<<5) // R/W
-#define S3C2410_UDC_OCSR1_FFLUSH       (1<<4) // R/W
-#define S3C2410_UDC_OCSR1_DERROR       (1<<3) // R
-#define S3C2410_UDC_OCSR1_OVRRUN       (1<<2) // R/W (clear only)
-#define S3C2410_UDC_OCSR1_PKTRDY       (1<<0) // R/W (clear only)
-
-#define S3C2410_UDC_OCSR2_AUTOCLR      (1<<7) // R/W
-#define S3C2410_UDC_OCSR2_ISO          (1<<6) // R/W
-#define S3C2410_UDC_OCSR2_DMAIEN       (1<<5) // R/W
-
-#define S3C2410_UDC_EP0_CSR_OPKRDY     (1<<0)
-#define S3C2410_UDC_EP0_CSR_IPKRDY     (1<<1)
-#define S3C2410_UDC_EP0_CSR_SENTSTL    (1<<2)
-#define S3C2410_UDC_EP0_CSR_DE         (1<<3)
-#define S3C2410_UDC_EP0_CSR_SE         (1<<4)
-#define S3C2410_UDC_EP0_CSR_SENDSTL    (1<<5)
-#define S3C2410_UDC_EP0_CSR_SOPKTRDY   (1<<6)
-#define S3C2410_UDC_EP0_CSR_SSE        (1<<7)
-
-#define S3C2410_UDC_MAXP_8             (1<<0)
-#define S3C2410_UDC_MAXP_16            (1<<1)
-#define S3C2410_UDC_MAXP_32            (1<<2)
-#define S3C2410_UDC_MAXP_64            (1<<3)
-
-
-#endif
diff --git a/include/asm-arm/arch-s3c2410/udc.h 
b/include/asm-arm/arch-s3c2410/udc.h
deleted file mode 100644
index b8aa6cb..0000000
--- a/include/asm-arm/arch-s3c2410/udc.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/* linux/include/asm-arm/arch-s3c2410/udc.h
- *
- * Copyright (c) 2005 Arnaud Patard <[EMAIL PROTECTED]>
- *
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- *
- *  Changelog:
- *     14-Mar-2005     RTP     Created file
- *     02-Aug-2005     RTP     File rename
- *     07-Sep-2005     BJD     Minor cleanups, changed cmd to enum
- *     18-Jan-2007     HMW     Add per-platform vbus_draw function
-*/
-
-#ifndef __ASM_ARM_ARCH_UDC_H
-#define __ASM_ARM_ARCH_UDC_H
-
-enum s3c2410_udc_cmd_e {
-       S3C2410_UDC_P_ENABLE    = 1,    /* Pull-up enable        */
-       S3C2410_UDC_P_DISABLE   = 2,    /* Pull-up disable       */
-       S3C2410_UDC_P_RESET     = 3,    /* UDC reset, in case of */
-};
-
-struct s3c2410_udc_mach_info {
-       void    (*udc_command)(enum s3c2410_udc_cmd_e);
-       void    (*vbus_draw)(unsigned int ma);
-       unsigned int vbus_pin;
-       unsigned char vbus_pin_inverted;
-};
-
-extern void __init s3c24xx_udc_set_platdata(struct s3c2410_udc_mach_info *);
-
-#endif /* __ASM_ARM_ARCH_UDC_H */
diff --git a/include/asm-arm/plat-s3c/regs-ac97.h 
b/include/asm-arm/plat-s3c/regs-ac97.h
new file mode 100644
index 0000000..b004dee
--- /dev/null
+++ b/include/asm-arm/plat-s3c/regs-ac97.h
@@ -0,0 +1,67 @@
+/* linux/include/asm-arm/arch-s3c2410/regs-ac97.h
+ *
+ * Copyright (c) 2006 Simtec Electronics <[EMAIL PROTECTED]>
+ *             http://www.simtec.co.uk/products/SWLINUX/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * S3C2440 AC97 Controller
+*/
+
+#ifndef __ASM_ARCH_REGS_AC97_H
+#define __ASM_ARCH_REGS_AC97_H __FILE__
+
+#define S3C_AC97_GLBCTRL                               (0x00)
+
+#define S3C_AC97_GLBCTRL_CODECREADYIE                  (1<<22)
+#define S3C_AC97_GLBCTRL_PCMOUTURIE                    (1<<21)
+#define S3C_AC97_GLBCTRL_PCMINORIE                     (1<<20)
+#define S3C_AC97_GLBCTRL_MICINORIE                     (1<<19)
+#define S3C_AC97_GLBCTRL_PCMOUTTIE                     (1<<18)
+#define S3C_AC97_GLBCTRL_PCMINTIE                      (1<<17)
+#define S3C_AC97_GLBCTRL_MICINTIE                      (1<<16)
+#define S3C_AC97_GLBCTRL_PCMOUTTM_OFF                  (0<<12)
+#define S3C_AC97_GLBCTRL_PCMOUTTM_PIO                  (1<<12)
+#define S3C_AC97_GLBCTRL_PCMOUTTM_DMA                  (2<<12)
+#define S3C_AC97_GLBCTRL_PCMOUTTM_MASK                 (3<<12)
+#define S3C_AC97_GLBCTRL_PCMINTM_OFF                   (0<<10)
+#define S3C_AC97_GLBCTRL_PCMINTM_PIO                   (1<<10)
+#define S3C_AC97_GLBCTRL_PCMINTM_DMA                   (2<<10)
+#define S3C_AC97_GLBCTRL_PCMINTM_MASK                  (3<<10)
+#define S3C_AC97_GLBCTRL_MICINTM_OFF                   (0<<8)
+#define S3C_AC97_GLBCTRL_MICINTM_PIO                   (1<<8)
+#define S3C_AC97_GLBCTRL_MICINTM_DMA                   (2<<8)
+#define S3C_AC97_GLBCTRL_MICINTM_MASK                  (3<<8)
+#define S3C_AC97_GLBCTRL_TRANSFERDATAENABLE            (1<<3)
+#define S3C_AC97_GLBCTRL_ACLINKON                      (1<<2)
+#define S3C_AC97_GLBCTRL_WARMRESET                     (1<<1)
+#define S3C_AC97_GLBCTRL_COLDRESET                     (1<<0)
+
+#define S3C_AC97_GLBSTAT                               (0x04)
+
+#define S3C_AC97_GLBSTAT_CODECREADY                    (1<<22)
+#define S3C_AC97_GLBSTAT_PCMOUTUR                      (1<<21)
+#define S3C_AC97_GLBSTAT_PCMINORI                      (1<<20)
+#define S3C_AC97_GLBSTAT_MICINORI                      (1<<19)
+#define S3C_AC97_GLBSTAT_PCMOUTTI                      (1<<18)
+#define S3C_AC97_GLBSTAT_PCMINTI                       (1<<17)
+#define S3C_AC97_GLBSTAT_MICINTI                       (1<<16)
+#define S3C_AC97_GLBSTAT_MAINSTATE_IDLE                        (0<<0)
+#define S3C_AC97_GLBSTAT_MAINSTATE_INIT                        (1<<0)
+#define S3C_AC97_GLBSTAT_MAINSTATE_READY               (2<<0)
+#define S3C_AC97_GLBSTAT_MAINSTATE_ACTIVE              (3<<0)
+#define S3C_AC97_GLBSTAT_MAINSTATE_LP                  (4<<0)
+#define S3C_AC97_GLBSTAT_MAINSTATE_WARM                        (5<<0)
+
+#define S3C_AC97_CODEC_CMD                             (0x08)
+
+#define S3C_AC97_CODEC_CMD_READ                                (1<<23)
+
+#define S3C_AC97_STAT                                  (0x0c)
+#define S3C_AC97_PCM_ADDR                              (0x10)
+#define S3C_AC97_PCM_DATA                              (0x18)
+#define S3C_AC97_MIC_DATA                              (0x1C)
+
+#endif /* __ASM_ARCH_REGS_AC97_H */
diff --git a/include/asm-arm/plat-s3c/regs-adc.h 
b/include/asm-arm/plat-s3c/regs-adc.h
new file mode 100644
index 0000000..c7f2319
--- /dev/null
+++ b/include/asm-arm/plat-s3c/regs-adc.h
@@ -0,0 +1,60 @@
+/* linux/include/asm-arm/arch-s3c2410/regs-adc.h
+ *
+ * Copyright (c) 2004 Shannon Holland <[EMAIL PROTECTED]>
+ *
+ * This program is free software; yosu can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * S3C2410 ADC registers
+*/
+
+#ifndef __ASM_ARCH_REGS_ADC_H
+#define __ASM_ARCH_REGS_ADC_H "regs-adc.h"
+
+#define S3C2410_ADCREG(x) (x)
+
+#define S3C2410_ADCCON    S3C2410_ADCREG(0x00)
+#define S3C2410_ADCTSC    S3C2410_ADCREG(0x04)
+#define S3C2410_ADCDLY    S3C2410_ADCREG(0x08)
+#define S3C2410_ADCDAT0           S3C2410_ADCREG(0x0C)
+#define S3C2410_ADCDAT1           S3C2410_ADCREG(0x10)
+
+
+/* ADCCON Register Bits */
+#define S3C2410_ADCCON_ECFLG           (1<<15)
+#define S3C2410_ADCCON_PRSCEN          (1<<14)
+#define S3C2410_ADCCON_PRSCVL(x)       (((x)&0xFF)<<6)
+#define S3C2410_ADCCON_PRSCVLMASK      (0xFF<<6)
+#define S3C2410_ADCCON_SELMUX(x)       (((x)&0x7)<<3)
+#define S3C2410_ADCCON_MUXMASK         (0x7<<3)
+#define S3C2410_ADCCON_STDBM           (1<<2)
+#define S3C2410_ADCCON_READ_START      (1<<1)
+#define S3C2410_ADCCON_ENABLE_START    (1<<0)
+#define S3C2410_ADCCON_STARTMASK       (0x3<<0)
+
+
+/* ADCTSC Register Bits */
+#define S3C2410_ADCTSC_YM_SEN          (1<<7)
+#define S3C2410_ADCTSC_YP_SEN          (1<<6)
+#define S3C2410_ADCTSC_XM_SEN          (1<<5)
+#define S3C2410_ADCTSC_XP_SEN          (1<<4)
+#define S3C2410_ADCTSC_PULL_UP_DISABLE (1<<3)
+#define S3C2410_ADCTSC_AUTO_PST                (1<<2)
+#define S3C2410_ADCTSC_XY_PST(x)       (((x)&0x3)<<0)
+
+/* ADCDAT0 Bits */
+#define S3C2410_ADCDAT0_UPDOWN         (1<<15)
+#define S3C2410_ADCDAT0_AUTO_PST       (1<<14)
+#define S3C2410_ADCDAT0_XY_PST         (0x3<<12)
+#define S3C2410_ADCDAT0_XPDATA_MASK    (0x03FF)
+
+/* ADCDAT1 Bits */
+#define S3C2410_ADCDAT1_UPDOWN         (1<<15)
+#define S3C2410_ADCDAT1_AUTO_PST       (1<<14)
+#define S3C2410_ADCDAT1_XY_PST         (0x3<<12)
+#define S3C2410_ADCDAT1_YPDATA_MASK    (0x03FF)
+
+#endif /* __ASM_ARCH_REGS_ADC_H */
+
+
diff --git a/include/asm-arm/plat-s3c24xx/regs-iis.h 
b/include/asm-arm/plat-s3c24xx/regs-iis.h
new file mode 100644
index 0000000..eaf7791
--- /dev/null
+++ b/include/asm-arm/plat-s3c24xx/regs-iis.h
@@ -0,0 +1,77 @@
+/* linux/include/asm-arm/arch-s3c2410/regs-iis.h
+ *
+ * Copyright (c) 2003 Simtec Electronics <[EMAIL PROTECTED]>
+ *                   http://www.simtec.co.uk/products/SWLINUX/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * S3C2410 IIS register definition
+*/
+
+#ifndef __ASM_ARCH_REGS_IIS_H
+#define __ASM_ARCH_REGS_IIS_H
+
+#define S3C2410_IISCON  (0x00)
+
+#define S3C2410_IISCON_LRINDEX   (1<<8)
+#define S3C2410_IISCON_TXFIFORDY  (1<<7)
+#define S3C2410_IISCON_RXFIFORDY  (1<<6)
+#define S3C2410_IISCON_TXDMAEN   (1<<5)
+#define S3C2410_IISCON_RXDMAEN   (1<<4)
+#define S3C2410_IISCON_TXIDLE    (1<<3)
+#define S3C2410_IISCON_RXIDLE    (1<<2)
+#define S3C2410_IISCON_PSCEN     (1<<1)
+#define S3C2410_IISCON_IISEN     (1<<0)
+
+#define S3C2410_IISMOD  (0x04)
+
+#define S3C2440_IISMOD_MPLL      (1<<9)
+#define S3C2410_IISMOD_SLAVE     (1<<8)
+#define S3C2410_IISMOD_NOXFER    (0<<6)
+#define S3C2410_IISMOD_RXMODE    (1<<6)
+#define S3C2410_IISMOD_TXMODE    (2<<6)
+#define S3C2410_IISMOD_TXRXMODE          (3<<6)
+#define S3C2410_IISMOD_LR_LLOW   (0<<5)
+#define S3C2410_IISMOD_LR_RLOW   (1<<5)
+#define S3C2410_IISMOD_IIS       (0<<4)
+#define S3C2410_IISMOD_MSB       (1<<4)
+#define S3C2410_IISMOD_8BIT      (0<<3)
+#define S3C2410_IISMOD_16BIT     (1<<3)
+#define S3C2410_IISMOD_BITMASK   (1<<3)
+#define S3C2410_IISMOD_256FS     (0<<2)
+#define S3C2410_IISMOD_384FS     (1<<2)
+#define S3C2410_IISMOD_16FS      (0<<0)
+#define S3C2410_IISMOD_32FS      (1<<0)
+#define S3C2410_IISMOD_48FS      (2<<0)
+#define S3C2410_IISMOD_FS_MASK   (3<<0)
+
+#define S3C2410_IISPSR         (0x08)
+#define S3C2410_IISPSR_INTMASK (31<<5)
+#define S3C2410_IISPSR_INTSHIFT        (5)
+#define S3C2410_IISPSR_EXTMASK (31<<0)
+#define S3C2410_IISPSR_EXTSHFIT        (0)
+
+#define S3C2410_IISFCON  (0x0c)
+
+#define S3C2410_IISFCON_TXDMA    (1<<15)
+#define S3C2410_IISFCON_RXDMA    (1<<14)
+#define S3C2410_IISFCON_TXENABLE  (1<<13)
+#define S3C2410_IISFCON_RXENABLE  (1<<12)
+#define S3C2410_IISFCON_TXMASK   (0x3f << 6)
+#define S3C2410_IISFCON_TXSHIFT          (6)
+#define S3C2410_IISFCON_RXMASK   (0x3f)
+#define S3C2410_IISFCON_RXSHIFT          (0)
+
+#define S3C2400_IISFCON_TXDMA     (1<<11)
+#define S3C2400_IISFCON_RXDMA     (1<<10)
+#define S3C2400_IISFCON_TXENABLE  (1<<9)
+#define S3C2400_IISFCON_RXENABLE  (1<<8)
+#define S3C2400_IISFCON_TXMASK   (0x07 << 4)
+#define S3C2400_IISFCON_TXSHIFT          (4)
+#define S3C2400_IISFCON_RXMASK   (0x07)
+#define S3C2400_IISFCON_RXSHIFT          (0)
+
+#define S3C2410_IISFIFO  (0x10)
+#endif /* __ASM_ARCH_REGS_IIS_H */
diff --git a/include/asm-arm/plat-s3c24xx/regs-spi.h 
b/include/asm-arm/plat-s3c24xx/regs-spi.h
new file mode 100644
index 0000000..4a499a1
--- /dev/null
+++ b/include/asm-arm/plat-s3c24xx/regs-spi.h
@@ -0,0 +1,54 @@
+/* linux/include/asm-arm/arch-s3c2410/regs-spi.h
+ *
+ * Copyright (c) 2004 Fetron GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * S3C2410 SPI register definition
+*/
+
+#ifndef __ASM_ARCH_REGS_SPI_H
+#define __ASM_ARCH_REGS_SPI_H
+
+#define S3C2410_SPI1   (0x20)
+#define S3C2412_SPI1   (0x100)
+
+#define S3C2410_SPCON  (0x00)
+
+#define S3C2410_SPCON_SMOD_DMA   (2<<5)        /* DMA mode */
+#define S3C2410_SPCON_SMOD_INT   (1<<5)        /* interrupt mode */
+#define S3C2410_SPCON_SMOD_POLL   (0<<5)       /* polling mode */
+#define S3C2410_SPCON_ENSCK      (1<<4)        /* Enable SCK */
+#define S3C2410_SPCON_MSTR       (1<<3)        /* Master/Slave select
+                                                  0: slave, 1: master */
+#define S3C2410_SPCON_CPOL_HIGH          (1<<2)        /* Clock polarity 
select */
+#define S3C2410_SPCON_CPOL_LOW   (0<<2)        /* Clock polarity select */
+
+#define S3C2410_SPCON_CPHA_FMTB          (1<<1)        /* Clock Phase Select */
+#define S3C2410_SPCON_CPHA_FMTA          (0<<1)        /* Clock Phase Select */
+
+#define S3C2410_SPCON_TAGD       (1<<0)        /* Tx auto garbage data mode */
+
+
+#define S3C2410_SPSTA   (0x04)
+
+#define S3C2410_SPSTA_DCOL       (1<<2)        /* Data Collision Error */
+#define S3C2410_SPSTA_MULD       (1<<1)        /* Multi Master Error */
+#define S3C2410_SPSTA_READY      (1<<0)        /* Data Tx/Rx ready */
+
+
+#define S3C2410_SPPIN   (0x08)
+
+#define S3C2410_SPPIN_ENMUL      (1<<2)        /* Multi Master Error detect */
+#define S3C2410_SPPIN_RESERVED   (1<<1)
+#define S3C2400_SPPIN_nCS        (1<<1)        /* SPI Card Select */
+#define S3C2410_SPPIN_KEEP       (1<<0)        /* Master Out keep */
+
+
+#define S3C2410_SPPRE   (0x0C)
+#define S3C2410_SPTDAT  (0x10)
+#define S3C2410_SPRDAT  (0x14)
+
+#endif /* __ASM_ARCH_REGS_SPI_H */
diff --git a/include/asm-arm/plat-s3c24xx/regs-udc.h 
b/include/asm-arm/plat-s3c24xx/regs-udc.h
new file mode 100644
index 0000000..e1e9805
--- /dev/null
+++ b/include/asm-arm/plat-s3c24xx/regs-udc.h
@@ -0,0 +1,153 @@
+/* linux/include/asm-arm/arch-s3c2410/regs-udc.h
+ *
+ * Copyright (C) 2004 Herbert Poetzl <[EMAIL PROTECTED]>
+ *
+ * This include file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+*/
+
+#ifndef __ASM_ARCH_REGS_UDC_H
+#define __ASM_ARCH_REGS_UDC_H
+
+#define S3C2410_USBDREG(x) (x)
+
+#define S3C2410_UDC_FUNC_ADDR_REG      S3C2410_USBDREG(0x0140)
+#define S3C2410_UDC_PWR_REG            S3C2410_USBDREG(0x0144)
+#define S3C2410_UDC_EP_INT_REG         S3C2410_USBDREG(0x0148)
+
+#define S3C2410_UDC_USB_INT_REG                S3C2410_USBDREG(0x0158)
+#define S3C2410_UDC_EP_INT_EN_REG      S3C2410_USBDREG(0x015c)
+
+#define S3C2410_UDC_USB_INT_EN_REG     S3C2410_USBDREG(0x016c)
+
+#define S3C2410_UDC_FRAME_NUM1_REG     S3C2410_USBDREG(0x0170)
+#define S3C2410_UDC_FRAME_NUM2_REG     S3C2410_USBDREG(0x0174)
+
+#define S3C2410_UDC_EP0_FIFO_REG       S3C2410_USBDREG(0x01c0)
+#define S3C2410_UDC_EP1_FIFO_REG       S3C2410_USBDREG(0x01c4)
+#define S3C2410_UDC_EP2_FIFO_REG       S3C2410_USBDREG(0x01c8)
+#define S3C2410_UDC_EP3_FIFO_REG       S3C2410_USBDREG(0x01cc)
+#define S3C2410_UDC_EP4_FIFO_REG       S3C2410_USBDREG(0x01d0)
+
+#define S3C2410_UDC_EP1_DMA_CON                S3C2410_USBDREG(0x0200)
+#define S3C2410_UDC_EP1_DMA_UNIT       S3C2410_USBDREG(0x0204)
+#define S3C2410_UDC_EP1_DMA_FIFO       S3C2410_USBDREG(0x0208)
+#define S3C2410_UDC_EP1_DMA_TTC_L      S3C2410_USBDREG(0x020c)
+#define S3C2410_UDC_EP1_DMA_TTC_M      S3C2410_USBDREG(0x0210)
+#define S3C2410_UDC_EP1_DMA_TTC_H      S3C2410_USBDREG(0x0214)
+
+#define S3C2410_UDC_EP2_DMA_CON                S3C2410_USBDREG(0x0218)
+#define S3C2410_UDC_EP2_DMA_UNIT       S3C2410_USBDREG(0x021c)
+#define S3C2410_UDC_EP2_DMA_FIFO       S3C2410_USBDREG(0x0220)
+#define S3C2410_UDC_EP2_DMA_TTC_L      S3C2410_USBDREG(0x0224)
+#define S3C2410_UDC_EP2_DMA_TTC_M      S3C2410_USBDREG(0x0228)
+#define S3C2410_UDC_EP2_DMA_TTC_H      S3C2410_USBDREG(0x022c)
+
+#define S3C2410_UDC_EP3_DMA_CON                S3C2410_USBDREG(0x0240)
+#define S3C2410_UDC_EP3_DMA_UNIT       S3C2410_USBDREG(0x0244)
+#define S3C2410_UDC_EP3_DMA_FIFO       S3C2410_USBDREG(0x0248)
+#define S3C2410_UDC_EP3_DMA_TTC_L      S3C2410_USBDREG(0x024c)
+#define S3C2410_UDC_EP3_DMA_TTC_M      S3C2410_USBDREG(0x0250)
+#define S3C2410_UDC_EP3_DMA_TTC_H      S3C2410_USBDREG(0x0254)
+
+#define S3C2410_UDC_EP4_DMA_CON                S3C2410_USBDREG(0x0258)
+#define S3C2410_UDC_EP4_DMA_UNIT       S3C2410_USBDREG(0x025c)
+#define S3C2410_UDC_EP4_DMA_FIFO       S3C2410_USBDREG(0x0260)
+#define S3C2410_UDC_EP4_DMA_TTC_L      S3C2410_USBDREG(0x0264)
+#define S3C2410_UDC_EP4_DMA_TTC_M      S3C2410_USBDREG(0x0268)
+#define S3C2410_UDC_EP4_DMA_TTC_H      S3C2410_USBDREG(0x026c)
+
+#define S3C2410_UDC_INDEX_REG          S3C2410_USBDREG(0x0178)
+
+/* indexed registers */
+
+#define S3C2410_UDC_MAXP_REG           S3C2410_USBDREG(0x0180)
+
+#define S3C2410_UDC_EP0_CSR_REG                S3C2410_USBDREG(0x0184)
+
+#define S3C2410_UDC_IN_CSR1_REG                S3C2410_USBDREG(0x0184)
+#define S3C2410_UDC_IN_CSR2_REG                S3C2410_USBDREG(0x0188)
+
+#define S3C2410_UDC_OUT_CSR1_REG       S3C2410_USBDREG(0x0190)
+#define S3C2410_UDC_OUT_CSR2_REG       S3C2410_USBDREG(0x0194)
+#define S3C2410_UDC_OUT_FIFO_CNT1_REG  S3C2410_USBDREG(0x0198)
+#define S3C2410_UDC_OUT_FIFO_CNT2_REG  S3C2410_USBDREG(0x019c)
+
+#define S3C2410_UDC_FUNCADDR_UPDATE    (1<<7)
+
+#define S3C2410_UDC_PWR_ISOUP          (1<<7) // R/W
+#define S3C2410_UDC_PWR_RESET          (1<<3) // R
+#define S3C2410_UDC_PWR_RESUME         (1<<2) // R/W
+#define S3C2410_UDC_PWR_SUSPEND                (1<<1) // R
+#define S3C2410_UDC_PWR_ENSUSPEND      (1<<0) // R/W
+
+#define S3C2410_UDC_PWR_DEFAULT                0x00
+
+#define S3C2410_UDC_INT_EP4            (1<<4) // R/W (clear only)
+#define S3C2410_UDC_INT_EP3            (1<<3) // R/W (clear only)
+#define S3C2410_UDC_INT_EP2            (1<<2) // R/W (clear only)
+#define S3C2410_UDC_INT_EP1            (1<<1) // R/W (clear only)
+#define S3C2410_UDC_INT_EP0            (1<<0) // R/W (clear only)
+
+#define S3C2410_UDC_USBINT_RESET       (1<<2) // R/W (clear only)
+#define S3C2410_UDC_USBINT_RESUME      (1<<1) // R/W (clear only)
+#define S3C2410_UDC_USBINT_SUSPEND     (1<<0) // R/W (clear only)
+
+#define S3C2410_UDC_INTE_EP4           (1<<4) // R/W
+#define S3C2410_UDC_INTE_EP3           (1<<3) // R/W
+#define S3C2410_UDC_INTE_EP2           (1<<2) // R/W
+#define S3C2410_UDC_INTE_EP1           (1<<1) // R/W
+#define S3C2410_UDC_INTE_EP0           (1<<0) // R/W
+
+#define S3C2410_UDC_USBINTE_RESET      (1<<2) // R/W
+#define S3C2410_UDC_USBINTE_SUSPEND    (1<<0) // R/W
+
+
+#define S3C2410_UDC_INDEX_EP0          (0x00)
+#define S3C2410_UDC_INDEX_EP1          (0x01) // ??
+#define S3C2410_UDC_INDEX_EP2          (0x02) // ??
+#define S3C2410_UDC_INDEX_EP3          (0x03) // ??
+#define S3C2410_UDC_INDEX_EP4          (0x04) // ??
+
+#define S3C2410_UDC_ICSR1_CLRDT                (1<<6) // R/W
+#define S3C2410_UDC_ICSR1_SENTSTL      (1<<5) // R/W (clear only)
+#define S3C2410_UDC_ICSR1_SENDSTL      (1<<4) // R/W
+#define S3C2410_UDC_ICSR1_FFLUSH       (1<<3) // W   (set only)
+#define S3C2410_UDC_ICSR1_UNDRUN       (1<<2) // R/W (clear only)
+#define S3C2410_UDC_ICSR1_PKTRDY       (1<<0) // R/W (set only)
+
+#define S3C2410_UDC_ICSR2_AUTOSET      (1<<7) // R/W
+#define S3C2410_UDC_ICSR2_ISO          (1<<6) // R/W
+#define S3C2410_UDC_ICSR2_MODEIN       (1<<5) // R/W
+#define S3C2410_UDC_ICSR2_DMAIEN       (1<<4) // R/W
+
+#define S3C2410_UDC_OCSR1_CLRDT                (1<<7) // R/W
+#define S3C2410_UDC_OCSR1_SENTSTL      (1<<6) // R/W (clear only)
+#define S3C2410_UDC_OCSR1_SENDSTL      (1<<5) // R/W
+#define S3C2410_UDC_OCSR1_FFLUSH       (1<<4) // R/W
+#define S3C2410_UDC_OCSR1_DERROR       (1<<3) // R
+#define S3C2410_UDC_OCSR1_OVRRUN       (1<<2) // R/W (clear only)
+#define S3C2410_UDC_OCSR1_PKTRDY       (1<<0) // R/W (clear only)
+
+#define S3C2410_UDC_OCSR2_AUTOCLR      (1<<7) // R/W
+#define S3C2410_UDC_OCSR2_ISO          (1<<6) // R/W
+#define S3C2410_UDC_OCSR2_DMAIEN       (1<<5) // R/W
+
+#define S3C2410_UDC_EP0_CSR_OPKRDY     (1<<0)
+#define S3C2410_UDC_EP0_CSR_IPKRDY     (1<<1)
+#define S3C2410_UDC_EP0_CSR_SENTSTL    (1<<2)
+#define S3C2410_UDC_EP0_CSR_DE         (1<<3)
+#define S3C2410_UDC_EP0_CSR_SE         (1<<4)
+#define S3C2410_UDC_EP0_CSR_SENDSTL    (1<<5)
+#define S3C2410_UDC_EP0_CSR_SOPKTRDY   (1<<6)
+#define S3C2410_UDC_EP0_CSR_SSE        (1<<7)
+
+#define S3C2410_UDC_MAXP_8             (1<<0)
+#define S3C2410_UDC_MAXP_16            (1<<1)
+#define S3C2410_UDC_MAXP_32            (1<<2)
+#define S3C2410_UDC_MAXP_64            (1<<3)
+
+
+#endif
diff --git a/include/asm-arm/plat-s3c24xx/udc.h 
b/include/asm-arm/plat-s3c24xx/udc.h
new file mode 100644
index 0000000..b8aa6cb
--- /dev/null
+++ b/include/asm-arm/plat-s3c24xx/udc.h
@@ -0,0 +1,36 @@
+/* linux/include/asm-arm/arch-s3c2410/udc.h
+ *
+ * Copyright (c) 2005 Arnaud Patard <[EMAIL PROTECTED]>
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ *
+ *  Changelog:
+ *     14-Mar-2005     RTP     Created file
+ *     02-Aug-2005     RTP     File rename
+ *     07-Sep-2005     BJD     Minor cleanups, changed cmd to enum
+ *     18-Jan-2007     HMW     Add per-platform vbus_draw function
+*/
+
+#ifndef __ASM_ARM_ARCH_UDC_H
+#define __ASM_ARM_ARCH_UDC_H
+
+enum s3c2410_udc_cmd_e {
+       S3C2410_UDC_P_ENABLE    = 1,    /* Pull-up enable        */
+       S3C2410_UDC_P_DISABLE   = 2,    /* Pull-up disable       */
+       S3C2410_UDC_P_RESET     = 3,    /* UDC reset, in case of */
+};
+
+struct s3c2410_udc_mach_info {
+       void    (*udc_command)(enum s3c2410_udc_cmd_e);
+       void    (*vbus_draw)(unsigned int ma);
+       unsigned int vbus_pin;
+       unsigned char vbus_pin_inverted;
+};
+
+extern void __init s3c24xx_udc_set_platdata(struct s3c2410_udc_mach_info *);
+
+#endif /* __ASM_ARM_ARCH_UDC_H */
-
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