Gitweb:     
http://git.kernel.org/git/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commit;h=637e9e13a1f87d414954c854bcf8c5b16dc6face
Commit:     637e9e13a1f87d414954c854bcf8c5b16dc6face
Parent:     3620fc1da28ad32d10d7c83eab33f48ec5b1da54
Author:     Randy Vinson <[EMAIL PROTECTED](none)>
AuthorDate: Fri Mar 23 15:43:37 2007 -0700
Committer:  Kumar Gala <[EMAIL PROTECTED]>
CommitDate: Mon Jul 23 22:35:12 2007 -0500

    [POWERPC] 85xxCDS: Make sure restart resets the PCI bus.
    
    The current 85xxCDS restart code fails to reset the PCI bus which can
    lead to odd behavior after the restart. This patch uses the VIA Super
    Southbridge to perform a PCI reset which will reset the entire system.
    NOTE: Since the VIA chip is behind a PCI-to-PCI bridge which can be
    disabled with a switch setting, it may not be possible to perform the
    PCI bus reset. In this case, the code defaults to the previous restart
    mechanism.
    
    Signed-off-by: Randy Vinson <[EMAIL PROTECTED]>
    Signed-off-by: Kumar Gala <[EMAIL PROTECTED]>
---
 arch/powerpc/platforms/85xx/mpc85xx_cds.c |   35 +++++++++++++++++++++++++++++
 1 files changed, 35 insertions(+), 0 deletions(-)

diff --git a/arch/powerpc/platforms/85xx/mpc85xx_cds.c 
b/arch/powerpc/platforms/85xx/mpc85xx_cds.c
index 81b7062..e77c869 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_cds.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_cds.c
@@ -69,6 +69,37 @@ static int mpc85xx_exclude_device(struct pci_controller 
*hose,
                return PCIBIOS_SUCCESSFUL;
 }
 
+static void mpc85xx_cds_restart(char *cmd)
+{
+       struct pci_dev *dev;
+       u_char tmp;
+
+       if ((dev = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686,
+                                       NULL))) {
+
+               /* Use the VIA Super Southbridge to force a PCI reset */
+               pci_read_config_byte(dev, 0x47, &tmp);
+               pci_write_config_byte(dev, 0x47, tmp | 1);
+
+               /* Flush the outbound PCI write queues */
+               pci_read_config_byte(dev, 0x47, &tmp);
+
+               /*
+                *  At this point, the harware reset should have triggered.
+                *  However, if it doesn't work for some mysterious reason,
+                *  just fall through to the default reset below.
+                */
+
+               pci_dev_put(dev);
+       }
+
+       /*
+        *  If we can't find the VIA chip (maybe the P2P bridge is disabled)
+        *  or the VIA chip reset didn't work, just use the default reset.
+        */
+       mpc85xx_restart(NULL);
+}
+
 static void __init mpc85xx_cds_pci_irq_fixup(struct pci_dev *dev)
 {
        u_char c;
@@ -304,7 +335,11 @@ define_machine(mpc85xx_cds) {
        .init_IRQ       = mpc85xx_cds_pic_init,
        .show_cpuinfo   = mpc85xx_cds_show_cpuinfo,
        .get_irq        = mpic_get_irq,
+#ifdef CONFIG_PCI
+       .restart        = mpc85xx_cds_restart,
+#else
        .restart        = mpc85xx_restart,
+#endif
        .calibrate_decr = generic_calibrate_decr,
        .progress       = udbg_progress,
        .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
-
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