Gitweb:     
http://git.kernel.org/git/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commit;h=6af012574207bd35455f4a4ba0437cf5b9deaee5
Commit:     6af012574207bd35455f4a4ba0437cf5b9deaee5
Parent:     8d7bc8f9d1c23fdfbf60a6554027c40d66e66d11
Author:     Randy Vinson <[EMAIL PROTECTED]>
AuthorDate: Tue Jul 17 16:37:12 2007 -0700
Committer:  Kumar Gala <[EMAIL PROTECTED]>
CommitDate: Tue Jul 24 10:31:55 2007 -0500

    [POWERPC] 85xxCDS: MPC8548 DTS cleanup.
    
    Added the P2P bridge present on the Arcadia base board and moved the VIA
    Southbridge behind the bridge to reflect its actual position in the bus
    organization. Added the RTC that's in the VIA Southbridge and expanded
    the ranges array for the SOC node to allow proper address translation of
    the RTC registers.
    
    Signed-off-by: Randy Vinson <[EMAIL PROTECTED]>
    Signed-off-by: Kumar Gala <[EMAIL PROTECTED]>
---
 arch/powerpc/boot/dts/mpc8548cds.dts |  124 ++++++++++++++++++++++++----------
 1 files changed, 89 insertions(+), 35 deletions(-)

diff --git a/arch/powerpc/boot/dts/mpc8548cds.dts 
b/arch/powerpc/boot/dts/mpc8548cds.dts
index 4770a5b..d215d21 100644
--- a/arch/powerpc/boot/dts/mpc8548cds.dts
+++ b/arch/powerpc/boot/dts/mpc8548cds.dts
@@ -44,8 +44,14 @@
                #size-cells = <1>;
                #interrupt-cells = <2>;
                device_type = "soc";
-               ranges = <0 e0000000 00100000>;
-               reg = <e0000000 00100000>;      // CCSRBAR 1M
+               ranges = <00001000 e0001000 000ff000
+                         80000000 80000000 10000000
+                         e2000000 e2000000 00800000
+                         90000000 90000000 10000000
+                         e2800000 e2800000 00800000
+                         a0000000 a0000000 20000000
+                         e3000000 e3000000 01000000>;
+               reg = <e0000000 00001000>;      // CCSRBAR
                bus-frequency = <0>;
 
                [EMAIL PROTECTED] {
@@ -162,8 +168,8 @@
                [EMAIL PROTECTED] {
                        device_type = "serial";
                        compatible = "ns16550";
-                       reg = <4500 100>;       // reg base, size
-                       clock-frequency = <0>;  // should we fill in in uboot?
+                       reg = <4500 100>;       // reg base, size
+                       clock-frequency = <0>;  // should we fill in in uboot?
                        interrupts = <2a 2>;
                        interrupt-parent = <&mpic>;
                };
@@ -172,7 +178,7 @@
                        device_type = "serial";
                        compatible = "ns16550";
                        reg = <4600 100>;       // reg base, size
-                       clock-frequency = <0>;  // should we fill in in uboot?
+                       clock-frequency = <0>;  // should we fill in in uboot?
                        interrupts = <2a 2>;
                        interrupt-parent = <&mpic>;
                };
@@ -183,8 +189,8 @@
                        fsl,has-rstcr;
                };
 
-               pci1: [EMAIL PROTECTED] {
-                       interrupt-map-mask = <1f800 0 0 7>;
+               [EMAIL PROTECTED] {
+                       interrupt-map-mask = <f800 0 0 7>;
                        interrupt-map = <
                                /* IDSEL 0x4 (PCIX Slot 2) */
                                02000 0 0 1 &mpic 0 1
@@ -244,19 +250,7 @@
                                0E000 0 0 1 &mpic 0 1
                                0E000 0 0 2 &mpic 1 1
                                0E000 0 0 3 &mpic 2 1
-                               0E000 0 0 4 &mpic 3 1
-
-                               /* bus 1 , idsel 0x2 Tsi310 bridge secondary */
-                               11000 0 0 1 &mpic 2 1
-                               11000 0 0 2 &mpic 3 1
-                               11000 0 0 3 &mpic 0 1
-                               11000 0 0 4 &mpic 1 1
-
-                               /* VIA chip */
-                               12000 0 0 1 &mpic 0 1
-                               12000 0 0 2 &mpic 1 1
-                               12000 0 0 3 &mpic 2 1
-                               12000 0 0 4 &mpic 3 1>;
+                               0E000 0 0 4 &mpic 3 1>;
 
                        interrupt-parent = <&mpic>;
                        interrupts = <18 2>;
@@ -271,18 +265,78 @@
                        compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
                        device_type = "pci";
 
-                       [EMAIL PROTECTED] {
-                               clock-frequency = <0>;
-                               interrupt-controller;
-                               device_type = "interrupt-controller";
-                               reg = <12000 0 0 0 1>;
-                               #address-cells = <0>;
-                               #interrupt-cells = <2>;
-                               built-in;
-                               compatible = "chrp,iic";
-                               big-endian;
-                               interrupts = <1>;
-                               interrupt-parent = <&pci1>;
+                       [EMAIL PROTECTED] {
+                               interrupt-map-mask = <f800 0 0 7>;
+                               interrupt-map = <
+
+                                       /* IDSEL 0x00 (PrPMC Site) */
+                                       0000 0 0 1 &mpic 0 1
+                                       0000 0 0 2 &mpic 1 1
+                                       0000 0 0 3 &mpic 2 1
+                                       0000 0 0 4 &mpic 3 1
+
+                                       /* IDSEL 0x04 (VIA chip) */
+                                       2000 0 0 1 &mpic 0 1
+                                       2000 0 0 2 &mpic 1 1
+                                       2000 0 0 3 &mpic 2 1
+                                       2000 0 0 4 &mpic 3 1
+
+                                       /* IDSEL 0x05 (8139) */
+                                       2800 0 0 1 &mpic 1 1
+
+                                       /* IDSEL 0x06 (Slot 6) */
+                                       3000 0 0 1 &mpic 2 1
+                                       3000 0 0 2 &mpic 3 1
+                                       3000 0 0 3 &mpic 0 1
+                                       3000 0 0 4 &mpic 1 1
+
+                                       /* IDESL 0x07 (Slot 7) */
+                                       3800 0 0 1 &mpic 3 1
+                                       3800 0 0 2 &mpic 0 1
+                                       3800 0 0 3 &mpic 1 1
+                                       3800 0 0 4 &mpic 2 1>;
+
+                               reg = <e000 0 0 0 0>;
+                               #interrupt-cells = <1>;
+                               #size-cells = <2>;
+                               #address-cells = <3>;
+                               ranges = <02000000 0 80000000
+                                         02000000 0 80000000
+                                         0 20000000
+                                         01000000 0 00000000
+                                         01000000 0 00000000
+                                         0 00080000>;
+                               clock-frequency = <1fca055>;
+
+                               [EMAIL PROTECTED] {
+                                       device_type = "isa";
+                                       #interrupt-cells = <2>;
+                                       #size-cells = <1>;
+                                       #address-cells = <2>;
+                                       reg = <2000 0 0 0 0>;
+                                       ranges = <1 0 01000000 0 0 00001000>;
+                                       interrupt-parent = <&i8259>;
+
+                                       i8259: [EMAIL PROTECTED] {
+                                               clock-frequency = <0>;
+                                               interrupt-controller;
+                                               device_type = 
"interrupt-controller";
+                                               reg = <1 20 2
+                                                      1 a0 2
+                                                      1 4d0 2>;
+                                               #address-cells = <0>;
+                                               #interrupt-cells = <2>;
+                                               built-in;
+                                               compatible = "chrp,iic";
+                                               interrupts = <0 1>;
+                                               interrupt-parent = <&mpic>;
+                                       };
+
+                                       [EMAIL PROTECTED] {
+                                               compatible = "pnpPNP,b00";
+                                               reg = <1 70 2>;
+                                       };
+                               };
                        };
                };
 
@@ -292,9 +346,9 @@
 
                                /* IDSEL 0x15 */
                                a800 0 0 1 &mpic b 1
-                               a800 0 0 2 &mpic b 1
-                               a800 0 0 3 &mpic b 1
-                               a800 0 0 4 &mpic b 1>;
+                               a800 0 0 2 &mpic 1 1
+                               a800 0 0 3 &mpic 2 1
+                               a800 0 0 4 &mpic 3 1>;
 
                        interrupt-parent = <&mpic>;
                        interrupts = <19 2>;
-
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