Gitweb:     
http://git.kernel.org/git/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commit;h=315a8e34f7c12609947f9b435faae451aaa5dd41
Commit:     315a8e34f7c12609947f9b435faae451aaa5dd41
Parent:     f695baf2df9e0413d3521661070103711545207a
Author:     Mike Frysinger <[EMAIL PROTECTED]>
AuthorDate: Tue Jul 24 15:58:41 2007 +0800
Committer:  Bryan Wu <[EMAIL PROTECTED]>
CommitDate: Tue Jul 24 15:58:41 2007 +0800

    Blackfin arch: setup aliases for some core Core A MMRs
    
    setup aliases for some core Core A MMRs to ease porting in cases
    where common code would actually want Core A (or Core B MMR is reserved)
    
    Signed-off-by: Mike Frysinger <[EMAIL PROTECTED]>
    Signed-off-by: Bryan Wu <[EMAIL PROTECTED]>
---
 arch/blackfin/mach-bf561/head.S             |   10 +++++-----
 include/asm-blackfin/mach-bf561/cdefBF561.h |    6 ++++++
 include/asm-blackfin/mach-bf561/defBF561.h  |    4 ++++
 3 files changed, 15 insertions(+), 5 deletions(-)

diff --git a/arch/blackfin/mach-bf561/head.S b/arch/blackfin/mach-bf561/head.S
index 2f08bcb..38650a6 100644
--- a/arch/blackfin/mach-bf561/head.S
+++ b/arch/blackfin/mach-bf561/head.S
@@ -440,15 +440,15 @@ ENTRY(_bfin_reset)
        SSYNC;
 
        /* make sure SYSCR is set to use BMODE */
-       P0.h = hi(SICA_SYSCR);
-       P0.l = lo(SICA_SYSCR);
-       R0.l = 0x20;
+       P0.h = hi(SYSCR);
+       P0.l = lo(SYSCR);
+       R0.l = 0x20;            /* on BF561, disable core b */
        W[P0] = R0.l;
        SSYNC;
 
        /* issue a system soft reset */
-       P1.h = hi(SICA_SWRST);
-       P1.l = lo(SICA_SWRST);
+       P1.h = hi(SWRST);
+       P1.l = lo(SWRST);
        R1.l = 0x0007;
        W[P1] = R1;
        SSYNC;
diff --git a/include/asm-blackfin/mach-bf561/cdefBF561.h 
b/include/asm-blackfin/mach-bf561/cdefBF561.h
index 1a8ec9e..6e87ab2 100644
--- a/include/asm-blackfin/mach-bf561/cdefBF561.h
+++ b/include/asm-blackfin/mach-bf561/cdefBF561.h
@@ -81,6 +81,12 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
 #define bfin_write_PLL_LOCKCNT(val)          bfin_write16(PLL_LOCKCNT,val)
 #define bfin_read_CHIPID()                   bfin_read32(CHIPID)
 
+/* For MMR's that are reserved on Core B, set up defines to better integrate 
with other ports */
+#define bfin_read_SWRST()                    bfin_read_SICA_SWRST()
+#define bfin_write_SWRST()                   bfin_write_SICA_SWRST()
+#define bfin_read_SYSCR()                    bfin_read_SICA_SYSCR()
+#define bfin_write_SYSCR()                   bfin_write_SICA_SYSCR()
+
 /* System Reset and Interrupt Controller registers for core A (0xFFC0 
0100-0xFFC0 01FF) */
 #define bfin_read_SICA_SWRST()               bfin_read16(SICA_SWRST)
 #define bfin_write_SICA_SWRST(val)           bfin_write16(SICA_SWRST,val)
diff --git a/include/asm-blackfin/mach-bf561/defBF561.h 
b/include/asm-blackfin/mach-bf561/defBF561.h
index 89150ec..0f2dc6e 100644
--- a/include/asm-blackfin/mach-bf561/defBF561.h
+++ b/include/asm-blackfin/mach-bf561/defBF561.h
@@ -52,6 +52,10 @@
 #define PLL_LOCKCNT            0xFFC00010      /* PLL Lock Count register 
(16-bit) */
 #define CHIPID                 0xFFC00014       /* Chip ID Register */
 
+/* For MMR's that are reserved on Core B, set up defines to better integrate 
with other ports */
+#define SWRST                   SICA_SWRST
+#define SYSCR                   SICA_SYSCR
+
 /* System Reset and Interrupt Controller registers for core A (0xFFC0 
0100-0xFFC0 01FF) */
 #define SICA_SWRST              0xFFC00100     /* Software Reset register */
 #define SICA_SYSCR              0xFFC00104     /* System Reset Configuration 
register */
-
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