Commit:     9c54ea95852a920720868d0e18bb4e9d645ea007
Parent:     ba0268a8b056f2ad846f1f8837a764c21bb6425e
Author:     Krzysztof Halasa <[EMAIL PROTECTED]>
AuthorDate: Tue Sep 11 15:24:12 2007 -0700
Committer:  Linus Torvalds <[EMAIL PROTECTED]>
CommitDate: Tue Sep 11 17:21:27 2007 -0700

    Subject: [PATCH] Intel FB pixel clock calculation fix
    Intel framebuffer mis-calculated pixel clocks.
    The pixel clock (and thus both H and V sync) will be slower than requested, 
    if you set the minimum allowed the display may not sync.  In case of really
    old CRT display it could theoretically damage it.
    I'm using it with PAL TV (using RGB input - SCART connector) and the bug
    prevented it from working at all (TV requirements are more strict and made 
    bug visible).
    Signed-off-by: Krzysztof Halasa <[EMAIL PROTECTED]>
    Cc: "Antonino A. Daplas" <[EMAIL PROTECTED]>
    Signed-off-by: Andrew Morton <[EMAIL PROTECTED]>
    Signed-off-by: Linus Torvalds <[EMAIL PROTECTED]>
 drivers/video/intelfb/intelfbhw.c |    6 +++---
 1 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/video/intelfb/intelfbhw.c 
index 16bc8d7..b21d0de 100644
--- a/drivers/video/intelfb/intelfbhw.c
+++ b/drivers/video/intelfb/intelfbhw.c
@@ -924,10 +924,10 @@ calc_pll_params(int index, int clock, u32 *retm1, u32 
*retm2, u32 *retn, u32 *re
                        if (m > pll->max_m)
                                m = pll->max_m - 1;
                        for (testm = m - 1; testm <= m; testm++) {
-                               f_out = calc_vclock3(index, m, n, p);
+                               f_out = calc_vclock3(index, testm, n, p);
                                if (splitm(index, testm, &m1, &m2)) {
-                                       WRN_MSG("cannot split m = %d\n", m);
-                                       n++;
+                                       WRN_MSG("cannot split m = %d\n",
+                                               testm);
                                if (clock > f_out)
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