Commit:     4827bbb06e4b59922c2b9bfb13ad1bf936bdebe5
Parent:     1bef7dc00caa7bcbff4fdb55e599e2591461fafa
Author:     Nick Piggin <[EMAIL PROTECTED]>
AuthorDate: Sat Sep 29 15:28:48 2007 +0200
Committer:  Linus Torvalds <[EMAIL PROTECTED]>
CommitDate: Sat Sep 29 09:13:59 2007 -0700

    i386: remove bogus comment about memory barrier
    The comment being removed by this patch is incorrect and misleading.
    In the following situation:
        1. load  ...
        2. store 1 -> X
        3. wmb
        4. rmb
        5. load  a <- Y
        6. store ...
    4 will only ensure ordering of 1 with 5.
    3 will only ensure ordering of 2 with 6.
    Further, a CPU with strictly in-order stores will still only provide that
    2 and 6 are ordered (effectively, it is the same as a weakly ordered CPU
    with wmb after every store).
    In all cases, 5 may still be executed before 2 is visible to other CPUs!
    The additional piece of the puzzle that mb() provides is the store/load
    ordering, which fundamentally cannot be achieved with any combination of
    rmb()s and wmb()s.
    This can be an unexpected result if one expected any sort of global ordering
    guarantee to barriers (eg. that the barriers themselves are sequentially
    consistent with other types of barriers).  However sfence or lfence barriers
    need only provide an ordering partial ordering of memory operations -- 
    that wmb may be implemented as nothing more than inserting a special barrier
    entry in the store queue, or, in the case of x86, it can be a noop as the 
    queue is in order. And an rmb may be implemented as a directive to prevent
    subsequent loads only so long as their are no previous outstanding loads 
    there could be stores still in store queues).
    I can actually see the occasional load/store being reordered around lfence 
    my core2. That doesn't prove my above assertions, but it does show the 
    is wrong (unless my program is -- can send it out by request).
       mb() and smp_mb() always have and always will require a full mfence
       or lock prefixed instruction on x86.  And we should remove this comment.
    Signed-off-by: Nick Piggin <[EMAIL PROTECTED]>
    Cc: Paul McKenney <[EMAIL PROTECTED]>
    Cc: David Howells <[EMAIL PROTECTED]>
    Cc: Andi Kleen <[EMAIL PROTECTED]>
    Signed-off-by: Linus Torvalds <[EMAIL PROTECTED]>
 include/asm-i386/system.h |    5 -----
 1 files changed, 0 insertions(+), 5 deletions(-)

diff --git a/include/asm-i386/system.h b/include/asm-i386/system.h
index 609756c..d69ba93 100644
--- a/include/asm-i386/system.h
+++ b/include/asm-i386/system.h
@@ -214,11 +214,6 @@ static inline unsigned long get_limit(unsigned long 
- * Actually only lfence would be needed for mb() because all stores done 
- * by the kernel should be already ordered. But keep a full barrier for now. 
- */
 #define mb() alternative("lock; addl $0,0(%%esp)", "mfence", X86_FEATURE_XMM2)
 #define rmb() alternative("lock; addl $0,0(%%esp)", "lfence", X86_FEATURE_XMM2)
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