Gitweb:     
http://git.kernel.org/git/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commit;h=553fdff633b1cb8cfccf554768444c5580a8d7f7
Commit:     553fdff633b1cb8cfccf554768444c5580a8d7f7
Parent:     868afce21fdadcecc7bde9263321065948508c56
Author:     David Gibson <[EMAIL PROTECTED]>
AuthorDate: Tue Aug 14 13:52:42 2007 +1000
Committer:  Paul Mackerras <[EMAIL PROTECTED]>
CommitDate: Fri Aug 17 11:02:06 2007 +1000

    [POWERPC] Improve robustness of the UIC cascade handler
    
    At present the cascade interrupt handler for the UIC (interrupt
    controller on 4xx embedded chips) will misbehave badly if it is called
    spuriously - that is if the handler is invoked when no interrupts are
    asserted in the child UIC.
    
    Although spurious interrupts shouldn't happen, it's good to behave
    robustly if they do.  This patch does so by checking for and ignoring
    spurious interrupts.
    
    Signed-off-by: Valentine Barshak <[EMAIL PROTECTED]>
    Signed-off-by: David Gibson <[EMAIL PROTECTED]>
    Acked-by: Josh Boyer <[EMAIL PROTECTED]>
    Signed-off-by: Paul Mackerras <[EMAIL PROTECTED]>
---
 arch/powerpc/sysdev/uic.c |    3 +++
 1 files changed, 3 insertions(+), 0 deletions(-)

diff --git a/arch/powerpc/sysdev/uic.c b/arch/powerpc/sysdev/uic.c
index 22c219e..47180b3 100644
--- a/arch/powerpc/sysdev/uic.c
+++ b/arch/powerpc/sysdev/uic.c
@@ -266,6 +266,9 @@ irqreturn_t uic_cascade(int virq, void *data)
        int subvirq;
 
        msr = mfdcr(uic->dcrbase + UIC_MSR);
+       if (!msr) /* spurious interrupt */
+               return IRQ_HANDLED;
+
        src = 32 - ffs(msr);
 
        subvirq = irq_linear_revmap(uic->irqhost, src);
-
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