Gitweb:     
http://git.kernel.org/git/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commit;h=06b74dd28fa607249c5e41e5f1f6dd1885fe0a0d
Commit:     06b74dd28fa607249c5e41e5f1f6dd1885fe0a0d
Parent:     21d2c925d3da6aabf9a0b34e95787202379f682a
Author:     Alan Cox <[EMAIL PROTECTED]>
AuthorDate: Wed Sep 26 15:23:17 2007 +0100
Committer:  Jeff Garzik <[EMAIL PROTECTED]>
CommitDate: Fri Oct 12 14:55:42 2007 -0400

    pata_pdc202xx_old MWDMA fixes, and notes
    
    I've been doing an audit of this driver to try and find out why we have
    problems with some Clevo boxes that use it. Didn't get anywhere other
    than to discover all the bug reporters I have use vmware, which may or
    may not be chance.
    
    In the process however I did find out our MWDMA2 performance was a bit
    low and code review showed the MWDMA0/2 timings are reversed due to a
    thinko in the table ordering
    
    Signed-off-by: Alan Cox <[EMAIL PROTECTED]>
    Signed-off-by: Jeff Garzik <[EMAIL PROTECTED]>
---
 drivers/ata/pata_pdc202xx_old.c |   15 ++++++++++-----
 1 files changed, 10 insertions(+), 5 deletions(-)

diff --git a/drivers/ata/pata_pdc202xx_old.c b/drivers/ata/pata_pdc202xx_old.c
index fd43500..65d9516 100644
--- a/drivers/ata/pata_pdc202xx_old.c
+++ b/drivers/ata/pata_pdc202xx_old.c
@@ -9,7 +9,7 @@
  * First cut with LBA48/ATAPI
  *
  * TODO:
- *     Channel interlock/reset on both required
+ *     Channel interlock/reset on both required ?
  */
 
 #include <linux/kernel.h>
@@ -22,7 +22,7 @@
 #include <linux/libata.h>
 
 #define DRV_NAME "pata_pdc202xx_old"
-#define DRV_VERSION "0.4.2"
+#define DRV_VERSION "0.4.3"
 
 static int pdc2026x_cable_detect(struct ata_port *ap)
 {
@@ -106,9 +106,9 @@ static void pdc202xx_set_dmamode(struct ata_port *ap, 
struct ata_device *adev)
                { 0x20, 0x01 }
        };
        static u8 mdma_timing[3][2] = {
-               { 0x60, 0x03 },
-               { 0x60, 0x04 },
                { 0xe0, 0x0f },
+               { 0x60, 0x04 },
+               { 0x60, 0x03 },
        };
        u8 r_bp, r_cp;
 
@@ -139,6 +139,9 @@ static void pdc202xx_set_dmamode(struct ata_port *ap, 
struct ata_device *adev)
  *
  *     In UDMA3 or higher we have to clock switch for the duration of the
  *     DMA transfer sequence.
+ *
+ *     Note: The host lock held by the libata layer protects
+ *     us from two channels both trying to set DMA bits at once
  */
 
 static void pdc2026x_bmdma_start(struct ata_queued_cmd *qc)
@@ -187,6 +190,9 @@ static void pdc2026x_bmdma_start(struct ata_queued_cmd *qc)
  *
  *     After a DMA completes we need to put the clock back to 33MHz for
  *     PIO timings.
+ *
+ *     Note: The host lock held by the libata layer protects
+ *     us from two channels both trying to set DMA bits at once
  */
 
 static void pdc2026x_bmdma_stop(struct ata_queued_cmd *qc)
@@ -206,7 +212,6 @@ static void pdc2026x_bmdma_stop(struct ata_queued_cmd *qc)
                iowrite32(0, atapi_reg);
                iowrite8(ioread8(clock) & ~sel66, clock);
        }
-       /* Check we keep host level locking here */
        /* Flip back to 33Mhz for PIO */
        if (adev->dma_mode >= XFER_UDMA_2)
                iowrite8(ioread8(clock) & ~sel66, clock);
-
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