Gitweb:     
http://git.kernel.org/git/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commit;h=cb7af21f7d370edb3a6a6d3e15cb17c8fd61591e
Commit:     cb7af21f7d370edb3a6a6d3e15cb17c8fd61591e
Parent:     c3af39758ce49b79570ab5ff2f64e0ea5fd82c9b
Author:     Paul Mundt <[EMAIL PROTECTED]>
AuthorDate: Thu Sep 27 18:18:39 2007 +0900
Committer:  Paul Mundt <[EMAIL PROTECTED]>
CommitDate: Thu Sep 27 18:18:39 2007 +0900

    sh: Use boot_cpu_data for CPU probe.
    
    This moves off of smp_processor_id() and only sets the probe
    information for the boot CPU directly. This will be copied out
    for the secondaries, so there's no reason to do this each time.
    
    This also allows for some header tidying.
    
    Signed-off-by: Paul Mundt <[EMAIL PROTECTED]>
---
 arch/sh/kernel/cpu/sh2/probe.c  |   19 ++---
 arch/sh/kernel/cpu/sh2a/probe.c |   18 ++--
 arch/sh/kernel/cpu/sh3/probe.c  |   47 +++++------
 arch/sh/kernel/cpu/sh4/probe.c  |  171 +++++++++++++++++++--------------------
 include/asm-sh/processor.h      |    1 -
 5 files changed, 126 insertions(+), 130 deletions(-)

diff --git a/arch/sh/kernel/cpu/sh2/probe.c b/arch/sh/kernel/cpu/sh2/probe.c
index abbf174..5916d90 100644
--- a/arch/sh/kernel/cpu/sh2/probe.c
+++ b/arch/sh/kernel/cpu/sh2/probe.c
@@ -10,26 +10,25 @@
  * for more details.
  */
 #include <linux/init.h>
-#include <linux/smp.h>
 #include <asm/processor.h>
 #include <asm/cache.h>
 
 int __init detect_cpu_and_cache_system(void)
 {
 #if defined(CONFIG_CPU_SUBTYPE_SH7619)
-       current_cpu_data.type                   = CPU_SH7619;
-       current_cpu_data.dcache.ways            = 4;
-       current_cpu_data.dcache.way_incr        = (1<<12);
-       current_cpu_data.dcache.sets            = 256;
-       current_cpu_data.dcache.entry_shift     = 4;
-       current_cpu_data.dcache.linesz          = L1_CACHE_BYTES;
-       current_cpu_data.dcache.flags           = 0;
+       boot_cpu_data.type                      = CPU_SH7619;
+       boot_cpu_data.dcache.ways               = 4;
+       boot_cpu_data.dcache.way_incr   = (1<<12);
+       boot_cpu_data.dcache.sets               = 256;
+       boot_cpu_data.dcache.entry_shift        = 4;
+       boot_cpu_data.dcache.linesz             = L1_CACHE_BYTES;
+       boot_cpu_data.dcache.flags              = 0;
 #endif
        /*
         * SH-2 doesn't have separate caches
         */
-       current_cpu_data.dcache.flags |= SH_CACHE_COMBINED;
-       current_cpu_data.icache = current_cpu_data.dcache;
+       boot_cpu_data.dcache.flags |= SH_CACHE_COMBINED;
+       boot_cpu_data.icache = boot_cpu_data.dcache;
 
        return 0;
 }
diff --git a/arch/sh/kernel/cpu/sh2a/probe.c b/arch/sh/kernel/cpu/sh2a/probe.c
index f455c35..6d02465 100644
--- a/arch/sh/kernel/cpu/sh2a/probe.c
+++ b/arch/sh/kernel/cpu/sh2a/probe.c
@@ -17,15 +17,15 @@
 int __init detect_cpu_and_cache_system(void)
 {
        /* Just SH7206 for now .. */
-       current_cpu_data.type                   = CPU_SH7206;
-       current_cpu_data.flags                  |= CPU_HAS_OP32;
+       boot_cpu_data.type                      = CPU_SH7206;
+       boot_cpu_data.flags                     |= CPU_HAS_OP32;
 
-       current_cpu_data.dcache.ways            = 4;
-       current_cpu_data.dcache.way_incr        = (1 << 11);
-       current_cpu_data.dcache.sets            = 128;
-       current_cpu_data.dcache.entry_shift     = 4;
-       current_cpu_data.dcache.linesz          = L1_CACHE_BYTES;
-       current_cpu_data.dcache.flags           = 0;
+       boot_cpu_data.dcache.ways               = 4;
+       boot_cpu_data.dcache.way_incr   = (1 << 11);
+       boot_cpu_data.dcache.sets               = 128;
+       boot_cpu_data.dcache.entry_shift        = 4;
+       boot_cpu_data.dcache.linesz             = L1_CACHE_BYTES;
+       boot_cpu_data.dcache.flags              = 0;
 
        /*
         * The icache is the same as the dcache as far as this setup is
@@ -33,7 +33,7 @@ int __init detect_cpu_and_cache_system(void)
         * lacks the U bit that the dcache has, none of this has any bearing
         * on the cache info.
         */
-       current_cpu_data.icache         = current_cpu_data.dcache;
+       boot_cpu_data.icache            = boot_cpu_data.dcache;
 
        return 0;
 }
diff --git a/arch/sh/kernel/cpu/sh3/probe.c b/arch/sh/kernel/cpu/sh3/probe.c
index 1a66cf6..bf579e0 100644
--- a/arch/sh/kernel/cpu/sh3/probe.c
+++ b/arch/sh/kernel/cpu/sh3/probe.c
@@ -50,47 +50,47 @@ int __init detect_cpu_and_cache_system(void)
 
        back_to_P1();
 
-       current_cpu_data.dcache.ways            = 4;
-       current_cpu_data.dcache.entry_shift     = 4;
-       current_cpu_data.dcache.linesz          = L1_CACHE_BYTES;
-       current_cpu_data.dcache.flags           = 0;
+       boot_cpu_data.dcache.ways               = 4;
+       boot_cpu_data.dcache.entry_shift        = 4;
+       boot_cpu_data.dcache.linesz             = L1_CACHE_BYTES;
+       boot_cpu_data.dcache.flags              = 0;
 
        /*
         * 7709A/7729 has 16K cache (256-entry), while 7702 has only
         * 2K(direct) 7702 is not supported (yet)
         */
        if (data0 == data1 && data2 == data3) { /* Shadow */
-               current_cpu_data.dcache.way_incr        = (1 << 11);
-               current_cpu_data.dcache.entry_mask      = 0x7f0;
-               current_cpu_data.dcache.sets            = 128;
-               current_cpu_data.type = CPU_SH7708;
+               boot_cpu_data.dcache.way_incr   = (1 << 11);
+               boot_cpu_data.dcache.entry_mask = 0x7f0;
+               boot_cpu_data.dcache.sets       = 128;
+               boot_cpu_data.type = CPU_SH7708;
 
-               current_cpu_data.flags |= CPU_HAS_MMU_PAGE_ASSOC;
+               boot_cpu_data.flags |= CPU_HAS_MMU_PAGE_ASSOC;
        } else {                                /* 7709A or 7729  */
-               current_cpu_data.dcache.way_incr        = (1 << 12);
-               current_cpu_data.dcache.entry_mask      = 0xff0;
-               current_cpu_data.dcache.sets            = 256;
-               current_cpu_data.type = CPU_SH7729;
+               boot_cpu_data.dcache.way_incr   = (1 << 12);
+               boot_cpu_data.dcache.entry_mask = 0xff0;
+               boot_cpu_data.dcache.sets       = 256;
+               boot_cpu_data.type = CPU_SH7729;
 
 #if defined(CONFIG_CPU_SUBTYPE_SH7706)
-               current_cpu_data.type = CPU_SH7706;
+               boot_cpu_data.type = CPU_SH7706;
 #endif
 #if defined(CONFIG_CPU_SUBTYPE_SH7710)
-               current_cpu_data.type = CPU_SH7710;
+               boot_cpu_data.type = CPU_SH7710;
 #endif
 #if defined(CONFIG_CPU_SUBTYPE_SH7712)
-               current_cpu_data.type = CPU_SH7712;
+               boot_cpu_data.type = CPU_SH7712;
 #endif
 #if defined(CONFIG_CPU_SUBTYPE_SH7720)
-               current_cpu_data.type = CPU_SH7720;
+               boot_cpu_data.type = CPU_SH7720;
 #endif
 #if defined(CONFIG_CPU_SUBTYPE_SH7705)
-               current_cpu_data.type = CPU_SH7705;
+               boot_cpu_data.type = CPU_SH7705;
 
 #if defined(CONFIG_SH7705_CACHE_32KB)
-               current_cpu_data.dcache.way_incr        = (1 << 13);
-               current_cpu_data.dcache.entry_mask      = 0x1ff0;
-               current_cpu_data.dcache.sets            = 512;
+               boot_cpu_data.dcache.way_incr   = (1 << 13);
+               boot_cpu_data.dcache.entry_mask = 0x1ff0;
+               boot_cpu_data.dcache.sets       = 512;
                ctrl_outl(CCR_CACHE_32KB, CCR3);
 #else
                ctrl_outl(CCR_CACHE_16KB, CCR3);
@@ -101,9 +101,8 @@ int __init detect_cpu_and_cache_system(void)
        /*
         * SH-3 doesn't have separate caches
         */
-       current_cpu_data.dcache.flags |= SH_CACHE_COMBINED;
-       current_cpu_data.icache = current_cpu_data.dcache;
+       boot_cpu_data.dcache.flags |= SH_CACHE_COMBINED;
+       boot_cpu_data.icache = boot_cpu_data.dcache;
 
        return 0;
 }
-
diff --git a/arch/sh/kernel/cpu/sh4/probe.c b/arch/sh/kernel/cpu/sh4/probe.c
index 8f318a4..21375d7 100644
--- a/arch/sh/kernel/cpu/sh4/probe.c
+++ b/arch/sh/kernel/cpu/sh4/probe.c
@@ -12,7 +12,6 @@
  */
 #include <linux/init.h>
 #include <linux/io.h>
-#include <linux/smp.h>
 #include <asm/processor.h>
 #include <asm/cache.h>
 
@@ -36,34 +35,34 @@ int __init detect_cpu_and_cache_system(void)
        /*
         * Setup some sane SH-4 defaults for the icache
         */
-       current_cpu_data.icache.way_incr        = (1 << 13);
-       current_cpu_data.icache.entry_shift     = 5;
-       current_cpu_data.icache.sets            = 256;
-       current_cpu_data.icache.ways            = 1;
-       current_cpu_data.icache.linesz          = L1_CACHE_BYTES;
+       boot_cpu_data.icache.way_incr           = (1 << 13);
+       boot_cpu_data.icache.entry_shift        = 5;
+       boot_cpu_data.icache.sets               = 256;
+       boot_cpu_data.icache.ways               = 1;
+       boot_cpu_data.icache.linesz             = L1_CACHE_BYTES;
 
        /*
         * And again for the dcache ..
         */
-       current_cpu_data.dcache.way_incr        = (1 << 14);
-       current_cpu_data.dcache.entry_shift     = 5;
-       current_cpu_data.dcache.sets            = 512;
-       current_cpu_data.dcache.ways            = 1;
-       current_cpu_data.dcache.linesz          = L1_CACHE_BYTES;
+       boot_cpu_data.dcache.way_incr           = (1 << 14);
+       boot_cpu_data.dcache.entry_shift        = 5;
+       boot_cpu_data.dcache.sets               = 512;
+       boot_cpu_data.dcache.ways               = 1;
+       boot_cpu_data.dcache.linesz             = L1_CACHE_BYTES;
 
        /*
         * Setup some generic flags we can probe on SH-4A parts
         */
        if (((pvr >> 16) & 0xff) == 0x10) {
                if ((cvr & 0x10000000) == 0)
-                       current_cpu_data.flags |= CPU_HAS_DSP;
+                       boot_cpu_data.flags |= CPU_HAS_DSP;
 
-               current_cpu_data.flags |= CPU_HAS_LLSC;
+               boot_cpu_data.flags |= CPU_HAS_LLSC;
        }
 
        /* FPU detection works for everyone */
        if ((cvr & 0x20000000) == 1)
-               current_cpu_data.flags |= CPU_HAS_FPU;
+               boot_cpu_data.flags |= CPU_HAS_FPU;
 
        /* Mask off the upper chip ID */
        pvr &= 0xffff;
@@ -74,140 +73,140 @@ int __init detect_cpu_and_cache_system(void)
         */
        switch (pvr) {
        case 0x205:
-               current_cpu_data.type = CPU_SH7750;
-               current_cpu_data.flags |= CPU_HAS_P2_FLUSH_BUG | CPU_HAS_FPU |
+               boot_cpu_data.type = CPU_SH7750;
+               boot_cpu_data.flags |= CPU_HAS_P2_FLUSH_BUG | CPU_HAS_FPU |
                                   CPU_HAS_PERF_COUNTER;
                break;
        case 0x206:
-               current_cpu_data.type = CPU_SH7750S;
-               current_cpu_data.flags |= CPU_HAS_P2_FLUSH_BUG | CPU_HAS_FPU |
+               boot_cpu_data.type = CPU_SH7750S;
+               boot_cpu_data.flags |= CPU_HAS_P2_FLUSH_BUG | CPU_HAS_FPU |
                                   CPU_HAS_PERF_COUNTER;
                break;
        case 0x1100:
-               current_cpu_data.type = CPU_SH7751;
-               current_cpu_data.flags |= CPU_HAS_FPU;
+               boot_cpu_data.type = CPU_SH7751;
+               boot_cpu_data.flags |= CPU_HAS_FPU;
                break;
        case 0x2001:
        case 0x2004:
-               current_cpu_data.type = CPU_SH7770;
-               current_cpu_data.icache.ways = 4;
-               current_cpu_data.dcache.ways = 4;
+               boot_cpu_data.type = CPU_SH7770;
+               boot_cpu_data.icache.ways = 4;
+               boot_cpu_data.dcache.ways = 4;
 
-               current_cpu_data.flags |= CPU_HAS_FPU | CPU_HAS_LLSC;
+               boot_cpu_data.flags |= CPU_HAS_FPU | CPU_HAS_LLSC;
                break;
        case 0x2006:
        case 0x200A:
                if (prr == 0x61)
-                       current_cpu_data.type = CPU_SH7781;
+                       boot_cpu_data.type = CPU_SH7781;
                else
-                       current_cpu_data.type = CPU_SH7780;
+                       boot_cpu_data.type = CPU_SH7780;
 
-               current_cpu_data.icache.ways = 4;
-               current_cpu_data.dcache.ways = 4;
+               boot_cpu_data.icache.ways = 4;
+               boot_cpu_data.dcache.ways = 4;
 
-               current_cpu_data.flags |= CPU_HAS_FPU | CPU_HAS_PERF_COUNTER |
+               boot_cpu_data.flags |= CPU_HAS_FPU | CPU_HAS_PERF_COUNTER |
                                   CPU_HAS_LLSC;
                break;
        case 0x3000:
        case 0x3003:
        case 0x3009:
-               current_cpu_data.type = CPU_SH7343;
-               current_cpu_data.icache.ways = 4;
-               current_cpu_data.dcache.ways = 4;
-               current_cpu_data.flags |= CPU_HAS_LLSC;
+               boot_cpu_data.type = CPU_SH7343;
+               boot_cpu_data.icache.ways = 4;
+               boot_cpu_data.dcache.ways = 4;
+               boot_cpu_data.flags |= CPU_HAS_LLSC;
                break;
        case 0x3004:
        case 0x3007:
-               current_cpu_data.type = CPU_SH7785;
-               current_cpu_data.icache.ways = 4;
-               current_cpu_data.dcache.ways = 4;
-               current_cpu_data.flags |= CPU_HAS_FPU | CPU_HAS_PERF_COUNTER |
+               boot_cpu_data.type = CPU_SH7785;
+               boot_cpu_data.icache.ways = 4;
+               boot_cpu_data.dcache.ways = 4;
+               boot_cpu_data.flags |= CPU_HAS_FPU | CPU_HAS_PERF_COUNTER |
                                          CPU_HAS_LLSC;
                break;
        case 0x3008:
                if (prr == 0xa0) {
-                       current_cpu_data.type = CPU_SH7722;
-                       current_cpu_data.icache.ways = 4;
-                       current_cpu_data.dcache.ways = 4;
-                       current_cpu_data.flags |= CPU_HAS_LLSC;
+                       boot_cpu_data.type = CPU_SH7722;
+                       boot_cpu_data.icache.ways = 4;
+                       boot_cpu_data.dcache.ways = 4;
+                       boot_cpu_data.flags |= CPU_HAS_LLSC;
                }
                break;
        case 0x4000:    /* 1st cut */
        case 0x4001:    /* 2nd cut */
-               current_cpu_data.type = CPU_SHX3;
-               current_cpu_data.icache.ways = 4;
-               current_cpu_data.dcache.ways = 4;
-               current_cpu_data.flags |= CPU_HAS_FPU | CPU_HAS_PERF_COUNTER |
+               boot_cpu_data.type = CPU_SHX3;
+               boot_cpu_data.icache.ways = 4;
+               boot_cpu_data.dcache.ways = 4;
+               boot_cpu_data.flags |= CPU_HAS_FPU | CPU_HAS_PERF_COUNTER |
                                          CPU_HAS_LLSC;
                break;
        case 0x8000:
-               current_cpu_data.type = CPU_ST40RA;
-               current_cpu_data.flags |= CPU_HAS_FPU;
+               boot_cpu_data.type = CPU_ST40RA;
+               boot_cpu_data.flags |= CPU_HAS_FPU;
                break;
        case 0x8100:
-               current_cpu_data.type = CPU_ST40GX1;
-               current_cpu_data.flags |= CPU_HAS_FPU;
+               boot_cpu_data.type = CPU_ST40GX1;
+               boot_cpu_data.flags |= CPU_HAS_FPU;
                break;
        case 0x700:
-               current_cpu_data.type = CPU_SH4_501;
-               current_cpu_data.icache.ways = 2;
-               current_cpu_data.dcache.ways = 2;
+               boot_cpu_data.type = CPU_SH4_501;
+               boot_cpu_data.icache.ways = 2;
+               boot_cpu_data.dcache.ways = 2;
                break;
        case 0x600:
-               current_cpu_data.type = CPU_SH4_202;
-               current_cpu_data.icache.ways = 2;
-               current_cpu_data.dcache.ways = 2;
-               current_cpu_data.flags |= CPU_HAS_FPU;
+               boot_cpu_data.type = CPU_SH4_202;
+               boot_cpu_data.icache.ways = 2;
+               boot_cpu_data.dcache.ways = 2;
+               boot_cpu_data.flags |= CPU_HAS_FPU;
                break;
        case 0x500 ... 0x501:
                switch (prr) {
                case 0x10:
-                       current_cpu_data.type = CPU_SH7750R;
+                       boot_cpu_data.type = CPU_SH7750R;
                        break;
                case 0x11:
-                       current_cpu_data.type = CPU_SH7751R;
+                       boot_cpu_data.type = CPU_SH7751R;
                        break;
                case 0x50 ... 0x5f:
-                       current_cpu_data.type = CPU_SH7760;
+                       boot_cpu_data.type = CPU_SH7760;
                        break;
                }
 
-               current_cpu_data.icache.ways = 2;
-               current_cpu_data.dcache.ways = 2;
+               boot_cpu_data.icache.ways = 2;
+               boot_cpu_data.dcache.ways = 2;
 
-               current_cpu_data.flags |= CPU_HAS_FPU;
+               boot_cpu_data.flags |= CPU_HAS_FPU;
 
                break;
        default:
-               current_cpu_data.type = CPU_SH_NONE;
+               boot_cpu_data.type = CPU_SH_NONE;
                break;
        }
 
 #ifdef CONFIG_SH_DIRECT_MAPPED
-       current_cpu_data.icache.ways = 1;
-       current_cpu_data.dcache.ways = 1;
+       boot_cpu_data.icache.ways = 1;
+       boot_cpu_data.dcache.ways = 1;
 #endif
 
 #ifdef CONFIG_CPU_HAS_PTEA
-       current_cpu_data.flags |= CPU_HAS_PTEA;
+       boot_cpu_data.flags |= CPU_HAS_PTEA;
 #endif
 
        /*
         * On anything that's not a direct-mapped cache, look to the CVR
         * for I/D-cache specifics.
         */
-       if (current_cpu_data.icache.ways > 1) {
+       if (boot_cpu_data.icache.ways > 1) {
                size = sizes[(cvr >> 20) & 0xf];
-               current_cpu_data.icache.way_incr        = (size >> 1);
-               current_cpu_data.icache.sets            = (size >> 6);
+               boot_cpu_data.icache.way_incr   = (size >> 1);
+               boot_cpu_data.icache.sets       = (size >> 6);
 
        }
 
        /* And the rest of the D-cache */
-       if (current_cpu_data.dcache.ways > 1) {
+       if (boot_cpu_data.dcache.ways > 1) {
                size = sizes[(cvr >> 16) & 0xf];
-               current_cpu_data.dcache.way_incr        = (size >> 1);
-               current_cpu_data.dcache.sets            = (size >> 6);
+               boot_cpu_data.dcache.way_incr   = (size >> 1);
+               boot_cpu_data.dcache.sets       = (size >> 6);
        }
 
        /*
@@ -215,7 +214,7 @@ int __init detect_cpu_and_cache_system(void)
         *
         * SH-4A's have an optional PIPT L2.
         */
-       if (current_cpu_data.flags & CPU_HAS_L2_CACHE) {
+       if (boot_cpu_data.flags & CPU_HAS_L2_CACHE) {
                /*
                 * Size calculation is much more sensible
                 * than it is for the L1.
@@ -226,22 +225,22 @@ int __init detect_cpu_and_cache_system(void)
 
                BUG_ON(!size);
 
-               current_cpu_data.scache.way_incr        = (1 << 16);
-               current_cpu_data.scache.entry_shift     = 5;
-               current_cpu_data.scache.ways            = 4;
-               current_cpu_data.scache.linesz          = L1_CACHE_BYTES;
+               boot_cpu_data.scache.way_incr           = (1 << 16);
+               boot_cpu_data.scache.entry_shift        = 5;
+               boot_cpu_data.scache.ways               = 4;
+               boot_cpu_data.scache.linesz             = L1_CACHE_BYTES;
 
-               current_cpu_data.scache.entry_mask      =
-                       (current_cpu_data.scache.way_incr -
-                        current_cpu_data.scache.linesz);
+               boot_cpu_data.scache.entry_mask =
+                       (boot_cpu_data.scache.way_incr -
+                        boot_cpu_data.scache.linesz);
 
-               current_cpu_data.scache.sets            = size /
-                       (current_cpu_data.scache.linesz *
-                        current_cpu_data.scache.ways);
+               boot_cpu_data.scache.sets       = size /
+                       (boot_cpu_data.scache.linesz *
+                        boot_cpu_data.scache.ways);
 
-               current_cpu_data.scache.way_size        =
-                       (current_cpu_data.scache.sets *
-                        current_cpu_data.scache.linesz);
+               boot_cpu_data.scache.way_size   =
+                       (boot_cpu_data.scache.sets *
+                        boot_cpu_data.scache.linesz);
        }
 
        return 0;
diff --git a/include/asm-sh/processor.h b/include/asm-sh/processor.h
index 9f3ee77..4f2922a 100644
--- a/include/asm-sh/processor.h
+++ b/include/asm-sh/processor.h
@@ -10,7 +10,6 @@
 #ifdef __KERNEL__
 
 #include <linux/compiler.h>
-#include <linux/smp.h>
 #include <asm/page.h>
 #include <asm/types.h>
 #include <asm/cache.h>
-
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