Gitweb:     
http://git.kernel.org/git/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commit;h=328329a7bda52a8ed413cd485211463581f7abab
Commit:     328329a7bda52a8ed413cd485211463581f7abab
Parent:     d1e44d9ce8589cc4ca0596989fe17130817ebec5
Author:     Anton Vorontsov <[EMAIL PROTECTED]>
AuthorDate: Tue Oct 16 01:27:47 2007 -0700
Committer:  Linus Torvalds <[EMAIL PROTECTED]>
CommitDate: Tue Oct 16 09:43:10 2007 -0700

    spi_mpc83xx handles other processors with QUICC engine
    
    Currently, all QE SPI controllers are almost the same comparing to
    MPC83xx's, thus let's use that driver for them.
    
    Tested to work on MPC85xx in loopback mode.
    
    Signed-off-by: Anton Vorontsov <[EMAIL PROTECTED]>
    Acked-by: Kumar Gala <[EMAIL PROTECTED]>
    Signed-off-by: David Brownell <[EMAIL PROTECTED]>
    Signed-off-by: Andrew Morton <[EMAIL PROTECTED]>
    Signed-off-by: Linus Torvalds <[EMAIL PROTECTED]>
---
 drivers/spi/Kconfig |   13 +++++++------
 1 files changed, 7 insertions(+), 6 deletions(-)

diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index b915711..a77ede5 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -124,16 +124,17 @@ config SPI_MPC52xx_PSC
          Controller in master SPI mode.
 
 config SPI_MPC83xx
-       tristate "Freescale MPC83xx SPI controller"
-       depends on SPI_MASTER && PPC_83xx && EXPERIMENTAL
+       tristate "Freescale MPC83xx/QUICC Engine SPI controller"
+       depends on SPI_MASTER && (PPC_83xx || QUICC_ENGINE) && EXPERIMENTAL
        select SPI_BITBANG
        help
-         This enables using the Freescale MPC83xx SPI controller in master
-         mode.
+         This enables using the Freescale MPC83xx and QUICC Engine SPI
+         controllers in master mode.
 
          Note, this driver uniquely supports the SPI controller on the MPC83xx
-         family of PowerPC processors.  The MPC83xx uses a simple set of shift
-         registers for data (opposed to the CPM based descriptor model).
+         family of PowerPC processors, plus processors with QUICC Engine
+         technology. This driver uses a simple set of shift registers for data
+         (opposed to the CPM based descriptor model).
 
 config SPI_OMAP_UWIRE
        tristate "OMAP1 MicroWire"
-
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