Gitweb:
http://git.kernel.org/git/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commit;h=64bfca5cd8c40fa138ad5db2513e8bcf8bd54ebd
Commit: 64bfca5cd8c40fa138ad5db2513e8bcf8bd54ebd
Parent: 985c30ef4d7c2a4f0e979a507a7e2f7f09b096c3
Author: Ralf Baechle <[EMAIL PROTECTED]>
AuthorDate: Mon Oct 15 16:35:45 2007 +0100
Committer: Ralf Baechle <[EMAIL PROTECTED]>
CommitDate: Tue Oct 16 18:23:49 2007 +0100
[MIPS] Cache: Provide more information on cache policy on bootup.
This should help making bug reports for the gadzillion of cores with all
their configuration and synthesis options more useful.
Signed-off-by: Ralf Baechle <[EMAIL PROTECTED]>
---
arch/mips/mm/c-r4k.c | 10 +++++++---
1 files changed, 7 insertions(+), 3 deletions(-)
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index 971f6c0..d708833 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -983,11 +983,15 @@ static void __init probe_pcache(void)
printk("Primary instruction cache %ldkB, %s, %s, linesize %d bytes.\n",
icache_size >> 10,
- cpu_has_vtag_icache ? "virtually tagged" : "physically tagged",
+ cpu_has_vtag_icache ? "VIVT" : "VIPT",
way_string[c->icache.ways], c->icache.linesz);
- printk("Primary data cache %ldkB, %s, linesize %d bytes.\n",
- dcache_size >> 10, way_string[c->dcache.ways], c->dcache.linesz);
+ printk("Primary data cache %ldkB, %s, %s, %s, linesize %d bytes\n",
+ dcache_size >> 10, way_string[c->dcache.ways],
+ (c->dcache.flags & MIPS_CACHE_PINDEX) ? "PIPT" : "VIPT",
+ (c->dcache.flags & MIPS_CACHE_ALIASES) ?
+ "cache aliases" : "no aliases",
+ c->dcache.linesz);
}
/*
-
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