Gitweb:
http://git.kernel.org/git/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commit;h=41241c17eb11df08efa81727f9c01225cd0f56b3
Commit: 41241c17eb11df08efa81727f9c01225cd0f56b3
Parent: 36208059c18cd5e8c89fc9037cb1a79e62733882
Author: Mike Frysinger <[EMAIL PROTECTED]>
AuthorDate: Tue Oct 30 12:03:47 2007 +0800
Committer: Bryan Wu <[EMAIL PROTECTED]>
CommitDate: Tue Oct 30 12:03:47 2007 +0800
Blackfin arch: Add missing definitions for BF561
Signed-off-by: Mike Frysinger <[EMAIL PROTECTED]>
Signed-off-by: Bryan Wu <[EMAIL PROTECTED]>
---
include/asm-blackfin/mach-bf561/defBF561.h | 3 +++
1 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/include/asm-blackfin/mach-bf561/defBF561.h
b/include/asm-blackfin/mach-bf561/defBF561.h
index bf7dc4e..7945e8a 100644
--- a/include/asm-blackfin/mach-bf561/defBF561.h
+++ b/include/asm-blackfin/mach-bf561/defBF561.h
@@ -55,6 +55,9 @@
/* For MMR's that are reserved on Core B, set up defines to better integrate
with other ports */
#define SWRST SICA_SWRST
#define SYSCR SICA_SYSCR
+#define RESET_DOUBLE (SWRST_DBL_FAULT_B|SWRST_DBL_FAULT_A)
+#define RESET_WDOG (SWRST_WDT_B|SWRST_WDT_A)
+#define RESET_SOFTWARE (SWRST_OCCURRED)
/* System Reset and Interrupt Controller registers for core A (0xFFC0
0100-0xFFC0 01FF) */
#define SICA_SWRST 0xFFC00100 /* Software Reset register */
-
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