Commit:     d8ecbb93bece05df84e654c296c3c81b3d347c2d
Parent:     7ac33417ecf8c012df0e957cfa0628a6a4347c7d
Author:     Kim Phillips <[EMAIL PROTECTED]>
AuthorDate: Mon Nov 19 19:04:43 2007 -0600
Committer:  Kumar Gala <[EMAIL PROTECTED]>
CommitDate: Mon Nov 19 22:03:16 2007 -0600

    [POWERPC] 83xx: mpc832x mds: Fix board PHY reset code
    currently the board-level PHY reset code for the mpc832x MDS messes with
    reset configuration words source settings which is plain wrong (it
    looks like this board code was cut-n-pasted from the mpc8360 mds code,
    which has the PHY reset bits in a different BCSR); this patch points
    the PHY reset code to the proper mpc832x mds PHY reset bits in the BCSR.
    Signed-off-by: Peter Van Ackeren <[EMAIL PROTECTED]>
    Signed-off-by: Kim Phillips <[EMAIL PROTECTED]>
    Signed-off-by: Kumar Gala <[EMAIL PROTECTED]>
 arch/powerpc/platforms/83xx/mpc832x_mds.c |    7 ++++---
 1 files changed, 4 insertions(+), 3 deletions(-)

diff --git a/arch/powerpc/platforms/83xx/mpc832x_mds.c 
index 972fa85..9e3bfcc 100644
--- a/arch/powerpc/platforms/83xx/mpc832x_mds.c
+++ b/arch/powerpc/platforms/83xx/mpc832x_mds.c
@@ -90,10 +90,11 @@ static void __init mpc832x_sys_setup_arch(void)
        if ((np = of_find_compatible_node(NULL, "network", "ucc_geth"))
                        != NULL){
-               /* Reset the Ethernet PHY */
-               bcsr_regs[9] &= ~0x20;
+               /* Reset the Ethernet PHYs */
+#define BCSR8_FETH_RST 0x50
+               bcsr_regs[8] &= ~BCSR8_FETH_RST;
-               bcsr_regs[9] |= 0x20;
+               bcsr_regs[8] |= BCSR8_FETH_RST;
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