Commit:     54fd6441e04696c046d93e4407a9e1ee9b874e51
Parent:     e1cca7e8d484390169777b423a7fe46c7021fec1
Author:     Pavel Kiryukhin <[EMAIL PROTECTED]>
AuthorDate: Tue Nov 27 19:20:47 2007 +0300
Committer:  Ralf Baechle <[EMAIL PROTECTED]>
CommitDate: Sat Dec 1 00:39:37 2007 +0000

    [MIPS] Fix use of smp_processor_id() in preemptible code.
    Freeing prom memory: 956kb freed
    Freeing firmware memory: 978944k freed
    Freeing unused kernel memory: 180k freed
    BUG: using smp_processor_id() in preemptible [00000000] code: swapper/1
    caller is r4k_dma_cache_wback_inv+0x144/0x2a0
    Call Trace:
     [<80117af8>] r4k_dma_cache_wback_inv+0x144/0x2a0
     [<802e4b84>] debug_smp_processor_id+0xd4/0xf0
     [<802e4b7c>] debug_smp_processor_id+0xcc/0xf0
    CONFIG_DEBUG_PREEMPT is enabled.
    Bug cause is blast_dcache_range() in preemptible code [in
    blast_dcache_range() is constructed via __BUILD_BLAST_CACHE_RANGE that
    uses cpu_dcache_line_size(). It uses current_cpu_data that use
    smp_processor_id() in turn. In case of CONFIG_DEBUG_PREEMPT
    smp_processor_id emits BUG if we are executing with preemption
    Cpu options of cpu0 are assumed to be the superset of all processors.
    Can I make the same assumptions for cache line size  and fix this
    issue the following way:
    Signed-off-by: Ralf Baechle <[EMAIL PROTECTED]>
 include/asm-mips/cpu-features.h |    6 +++---
 1 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/include/asm-mips/cpu-features.h b/include/asm-mips/cpu-features.h
index f6bd308..5ea701f 100644
--- a/include/asm-mips/cpu-features.h
+++ b/include/asm-mips/cpu-features.h
@@ -207,13 +207,13 @@
 #ifndef cpu_dcache_line_size
-#define cpu_dcache_line_size() current_cpu_data.dcache.linesz
+#define cpu_dcache_line_size() cpu_data[0].dcache.linesz
 #ifndef cpu_icache_line_size
-#define cpu_icache_line_size() current_cpu_data.icache.linesz
+#define cpu_icache_line_size() cpu_data[0].icache.linesz
 #ifndef cpu_scache_line_size
-#define cpu_scache_line_size() current_cpu_data.scache.linesz
+#define cpu_scache_line_size() cpu_data[0].scache.linesz
 #endif /* __ASM_CPU_FEATURES_H */
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