Commit:     0487de91427925e7c43debeb948bdf53b10ef32c
Parent:     c2a04c4f0e1b09b58d7279e2facd306c40583ec1
Author:     Dmitri Vorobiev <[EMAIL PROTECTED]>
AuthorDate: Tue Jan 15 00:27:46 2008 +0300
Committer:  Ralf Baechle <[EMAIL PROTECTED]>
CommitDate: Tue Jan 22 00:35:23 2008 +0000

    [MIPS] Malta: Fix reading the PCI clock frequency on big-endian
    The JMPRS register on Malta boards keeps a 32-bit CPU-endian
    value. The readw() function assumes that the value it reads is a
    little-endian 16-bit number. Therefore, using readw() to obtain
    the value of the JMPRS register is a mistake. This error leads
    to incorrect reading of the PCI clock frequency on big-endian
    during board start-up.
    Change readw() to __raw_readl().
    This was tested by injecting a call to printk() and verifying
    that the value of the jmpr variable was consistent with current
    setting of the JP4 "PCI CLK" jumper.
    Signed-off-by: Dmitri Vorobiev <[EMAIL PROTECTED]>
    Signed-off-by: Ralf Baechle <[EMAIL PROTECTED]>
 arch/mips/mips-boards/malta/malta_setup.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/mips/mips-boards/malta/malta_setup.c 
index 9a2636e..bc43a5c 100644
--- a/arch/mips/mips-boards/malta/malta_setup.c
+++ b/arch/mips/mips-boards/malta/malta_setup.c
@@ -149,7 +149,7 @@ void __init plat_mem_setup(void)
        /* Check PCI clock */
                unsigned int __iomem *jmpr_p = (unsigned int *) 
ioremap(MALTA_JMPRS_REG, sizeof(unsigned int));
-               int jmpr = (readw(jmpr_p) >> 2) & 0x07;
+               int jmpr = (__raw_readl(jmpr_p) >> 2) & 0x07;
                static const int pciclocks[] __initdata = {
                        33, 20, 25, 30, 12, 16, 37, 10
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