Commit:     3ebb5a2b44b02bddd5fbf0f29d71f1df6146c2c3
Parent:     15754bf98ff564e8bb5296c7f5e67bc59b5700aa
Author:     Nicolas Pitre <[EMAIL PROTECTED]>
AuthorDate: Wed Oct 31 15:31:48 2007 -0400
Committer:  Russell King <[EMAIL PROTECTED]>
CommitDate: Sat Jan 26 15:03:40 2008 +0000

    [ARM] add Feroceon support to compressed/head.S
    The cache replacement policy on the Feroceon core doesn't guarantee
    that reading through a linear chunk of memory flushes the entire cache.
    This is however what the default method for ARMv5TE cores does.
    Although the Feroceon is an ARMv5TE core, it implements the same
    cache handling instructions as the ARMv5TEJ cores, and must use it for
    proper cache flush.
    Signed-off-by: Nicolas Pitre <[EMAIL PROTECTED]>
    Acked-by: Russell King <[EMAIL PROTECTED]>
 arch/arm/boot/compressed/head.S |    6 ++++++
 1 files changed, 6 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
index 2073bf0..3c2c8f2 100644
--- a/arch/arm/boot/compressed/head.S
+++ b/arch/arm/boot/compressed/head.S
@@ -623,6 +623,12 @@ proc_types:
                b       __armv4_mmu_cache_off
                b       __armv4_mmu_cache_flush
+               .word   0x56055310              @ Feroceon
+               .word   0xfffffff0
+               b       __armv4_mmu_cache_on
+               b       __armv4_mmu_cache_off
+               b       __armv5tej_mmu_cache_flush
                @ These match on the architecture ID
                .word   0x00020000              @ ARMv4T
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