Gitweb:     
http://git.kernel.org/git/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commit;h=8785a8fbd5a1624dbabd7c782524450e902b722e
Commit:     8785a8fbd5a1624dbabd7c782524450e902b722e
Parent:     7664c400cc994542a27d1bacde54673880e7e179
Author:     Russell King <[EMAIL PROTECTED]>
AuthorDate: Mon Jan 14 17:02:33 2008 +0000
Committer:  Russell King <[EMAIL PROTECTED]>
CommitDate: Sat Jan 26 15:07:54 2008 +0000

    [ARM] pxa: move memory controller registers into pxa2xx-regs.h
    
    PXA3 has a different memory controller from PXA2 platforms.  Avoid
    clashing definitions by moving the PXA2 definitions to pxa2xx-regs.h
    
    Signed-off-by: Russell King <[EMAIL PROTECTED]>
---
 arch/arm/mach-pxa/cpu-pxa.c            |    1 +
 arch/arm/mach-pxa/lpd270.c             |    1 +
 arch/arm/mach-pxa/lubbock.c            |    1 +
 arch/arm/mach-pxa/mainstone.c          |    1 +
 arch/arm/mach-pxa/pxa27x.c             |    1 +
 arch/arm/mach-pxa/sleep.S              |    1 +
 drivers/pcmcia/pxa2xx_base.c           |    1 +
 include/asm-arm/arch-pxa/pxa-regs.h    |   63 ------------------------
 include/asm-arm/arch-pxa/pxa2xx-regs.h |   84 ++++++++++++++++++++++++++++++++
 9 files changed, 91 insertions(+), 63 deletions(-)

diff --git a/arch/arm/mach-pxa/cpu-pxa.c b/arch/arm/mach-pxa/cpu-pxa.c
index 18d042b..cbc583b 100644
--- a/arch/arm/mach-pxa/cpu-pxa.c
+++ b/arch/arm/mach-pxa/cpu-pxa.c
@@ -39,6 +39,7 @@
 
 #include <asm/hardware.h>
 #include <asm/arch/pxa-regs.h>
+#include <asm/arch/pxa2xx-regs.h>
 
 #ifdef DEBUG
 static unsigned int freq_debug;
diff --git a/arch/arm/mach-pxa/lpd270.c b/arch/arm/mach-pxa/lpd270.c
index 78ebad0..afa62ff 100644
--- a/arch/arm/mach-pxa/lpd270.c
+++ b/arch/arm/mach-pxa/lpd270.c
@@ -38,6 +38,7 @@
 #include <asm/mach/flash.h>
 
 #include <asm/arch/pxa-regs.h>
+#include <asm/arch/pxa2xx-regs.h>
 #include <asm/arch/lpd270.h>
 #include <asm/arch/audio.h>
 #include <asm/arch/pxafb.h>
diff --git a/arch/arm/mach-pxa/lubbock.c b/arch/arm/mach-pxa/lubbock.c
index 1b9290c..a75594b 100644
--- a/arch/arm/mach-pxa/lubbock.c
+++ b/arch/arm/mach-pxa/lubbock.c
@@ -41,6 +41,7 @@
 #include <asm/hardware/sa1111.h>
 
 #include <asm/arch/pxa-regs.h>
+#include <asm/arch/pxa2xx-regs.h>
 #include <asm/arch/lubbock.h>
 #include <asm/arch/udc.h>
 #include <asm/arch/irda.h>
diff --git a/arch/arm/mach-pxa/mainstone.c b/arch/arm/mach-pxa/mainstone.c
index 237459b..06e1360 100644
--- a/arch/arm/mach-pxa/mainstone.c
+++ b/arch/arm/mach-pxa/mainstone.c
@@ -39,6 +39,7 @@
 #include <asm/mach/flash.h>
 
 #include <asm/arch/pxa-regs.h>
+#include <asm/arch/pxa2xx-regs.h>
 #include <asm/arch/mainstone.h>
 #include <asm/arch/audio.h>
 #include <asm/arch/pxafb.h>
diff --git a/arch/arm/mach-pxa/pxa27x.c b/arch/arm/mach-pxa/pxa27x.c
index ec7597b..b9fa5ec 100644
--- a/arch/arm/mach-pxa/pxa27x.c
+++ b/arch/arm/mach-pxa/pxa27x.c
@@ -21,6 +21,7 @@
 #include <asm/irq.h>
 #include <asm/arch/irqs.h>
 #include <asm/arch/pxa-regs.h>
+#include <asm/arch/pxa2xx-regs.h>
 #include <asm/arch/ohci.h>
 #include <asm/arch/pm.h>
 #include <asm/arch/dma.h>
diff --git a/arch/arm/mach-pxa/sleep.S b/arch/arm/mach-pxa/sleep.S
index d044772..f33d0c4 100644
--- a/arch/arm/mach-pxa/sleep.S
+++ b/arch/arm/mach-pxa/sleep.S
@@ -16,6 +16,7 @@
 #include <asm/hardware.h>
 
 #include <asm/arch/pxa-regs.h>
+#include <asm/arch/pxa2xx-regs.h>
 
 #define MDREFR_KDIV    0x200a4000      // all banks
 #define CCCR_SLEEP     0x00000107      // L=7 2N=2 A=0 PPDIS=0 CPDIS=0
diff --git a/drivers/pcmcia/pxa2xx_base.c b/drivers/pcmcia/pxa2xx_base.c
index 874923f..e439044 100644
--- a/drivers/pcmcia/pxa2xx_base.c
+++ b/drivers/pcmcia/pxa2xx_base.c
@@ -29,6 +29,7 @@
 #include <asm/irq.h>
 #include <asm/system.h>
 #include <asm/arch/pxa-regs.h>
+#include <asm/arch/pxa2xx-regs.h>
 
 #include <pcmcia/cs_types.h>
 #include <pcmcia/ss.h>
diff --git a/include/asm-arm/arch-pxa/pxa-regs.h 
b/include/asm-arm/arch-pxa/pxa-regs.h
index f7809ea..442494d 100644
--- a/include/asm-arm/arch-pxa/pxa-regs.h
+++ b/include/asm-arm/arch-pxa/pxa-regs.h
@@ -1848,71 +1848,8 @@
 
 #define LDCMD_PAL      (1 << 26)       /* instructs DMA to load palette buffer 
*/
 
-/*
- * Memory controller
- */
-
-#define MDCNFG         __REG(0x48000000)  /* SDRAM Configuration Register 0 */
-#define MDREFR         __REG(0x48000004)  /* SDRAM Refresh Control Register */
-#define MSC0           __REG(0x48000008)  /* Static Memory Control Register 0 
*/
-#define MSC1           __REG(0x4800000C)  /* Static Memory Control Register 1 
*/
-#define MSC2           __REG(0x48000010)  /* Static Memory Control Register 2 
*/
-#define MECR           __REG(0x48000014)  /* Expansion Memory (PCMCIA/Compact 
Flash) Bus Configuration */
-#define SXLCR          __REG(0x48000018)  /* LCR value to be written to 
SDRAM-Timing Synchronous Flash */
-#define SXCNFG         __REG(0x4800001C)  /* Synchronous Static Memory Control 
Register */
-#define SXMRS          __REG(0x48000024)  /* MRS value to be written to 
Synchronous Flash or SMROM */
-#define MCMEM0         __REG(0x48000028)  /* Card interface Common Memory 
Space Socket 0 Timing */
-#define MCMEM1         __REG(0x4800002C)  /* Card interface Common Memory 
Space Socket 1 Timing */
-#define MCATT0         __REG(0x48000030)  /* Card interface Attribute Space 
Socket 0 Timing Configuration */
-#define MCATT1         __REG(0x48000034)  /* Card interface Attribute Space 
Socket 1 Timing Configuration */
-#define MCIO0          __REG(0x48000038)  /* Card interface I/O Space Socket 0 
Timing Configuration */
-#define MCIO1          __REG(0x4800003C)  /* Card interface I/O Space Socket 1 
Timing Configuration */
-#define MDMRS          __REG(0x48000040)  /* MRS value to be written to SDRAM 
*/
-#define BOOT_DEF       __REG(0x48000044)  /* Read-Only Boot-Time Register. 
Contains BOOT_SEL and PKG_SEL */
-
-/*
- * More handy macros for PCMCIA
- *
- * Arg is socket number
- */
-#define MCMEM(s)       __REG2(0x48000028, (s)<<2 )  /* Card interface Common 
Memory Space Socket s Timing */
-#define MCATT(s)       __REG2(0x48000030, (s)<<2 )  /* Card interface 
Attribute Space Socket s Timing Configuration */
-#define MCIO(s)                __REG2(0x48000038, (s)<<2 )  /* Card interface 
I/O Space Socket s Timing Configuration */
-
-/* MECR register defines */
-#define MECR_NOS       (1 << 0)        /* Number Of Sockets: 0 -> 1 sock, 1 -> 
2 sock */
-#define MECR_CIT       (1 << 1)        /* Card Is There: 0 -> no card, 1 -> 
card inserted */
-
-#define MDREFR_K0DB4   (1 << 29)       /* SDCLK0 Divide by 4 Control/Status */
-#define MDREFR_K2FREE  (1 << 25)       /* SDRAM Free-Running Control */
-#define MDREFR_K1FREE  (1 << 24)       /* SDRAM Free-Running Control */
-#define MDREFR_K0FREE  (1 << 23)       /* SDRAM Free-Running Control */
-#define MDREFR_SLFRSH  (1 << 22)       /* SDRAM Self-Refresh Control/Status */
-#define MDREFR_APD     (1 << 20)       /* SDRAM/SSRAM Auto-Power-Down Enable */
-#define MDREFR_K2DB2   (1 << 19)       /* SDCLK2 Divide by 2 Control/Status */
-#define MDREFR_K2RUN   (1 << 18)       /* SDCLK2 Run Control/Status */
-#define MDREFR_K1DB2   (1 << 17)       /* SDCLK1 Divide by 2 Control/Status */
-#define MDREFR_K1RUN   (1 << 16)       /* SDCLK1 Run Control/Status */
-#define MDREFR_E1PIN   (1 << 15)       /* SDCKE1 Level Control/Status */
-#define MDREFR_K0DB2   (1 << 14)       /* SDCLK0 Divide by 2 Control/Status */
-#define MDREFR_K0RUN   (1 << 13)       /* SDCLK0 Run Control/Status */
-#define MDREFR_E0PIN   (1 << 12)       /* SDCKE0 Level Control/Status */
-
-
 #ifdef CONFIG_PXA27x
 
-#define ARB_CNTRL      __REG(0x48000048)  /* Arbiter Control Register */
-
-#define ARB_DMA_SLV_PARK       (1<<31)    /* Be parked with DMA slave when 
idle */
-#define ARB_CI_PARK            (1<<30)    /* Be parked with Camera Interface 
when idle */
-#define ARB_EX_MEM_PARK        (1<<29)    /* Be parked with external MEMC when 
idle */
-#define ARB_INT_MEM_PARK       (1<<28)    /* Be parked with internal MEMC when 
idle */
-#define ARB_USB_PARK           (1<<27)    /* Be parked with USB when idle */
-#define ARB_LCD_PARK           (1<<26)    /* Be parked with LCD when idle */
-#define ARB_DMA_PARK           (1<<25)    /* Be parked with DMA when idle */
-#define ARB_CORE_PARK          (1<<24)    /* Be parked with core when idle */
-#define ARB_LOCK_FLAG          (1<<23)    /* Only Locking masters gain access 
to the bus */
-
 /*
  * Keypad
  */
diff --git a/include/asm-arm/arch-pxa/pxa2xx-regs.h 
b/include/asm-arm/arch-pxa/pxa2xx-regs.h
new file mode 100644
index 0000000..9553b54
--- /dev/null
+++ b/include/asm-arm/arch-pxa/pxa2xx-regs.h
@@ -0,0 +1,84 @@
+/*
+ *  linux/include/asm-arm/arch-pxa/pxa2xx-regs.h
+ *
+ *  Taken from pxa-regs.h by Russell King
+ *
+ *  Author:    Nicolas Pitre
+ *  Copyright: MontaVista Software Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __PXA2XX_REGS_H
+#define __PXA2XX_REGS_H
+
+/*
+ * Memory controller
+ */
+
+#define MDCNFG         __REG(0x48000000)  /* SDRAM Configuration Register 0 */
+#define MDREFR         __REG(0x48000004)  /* SDRAM Refresh Control Register */
+#define MSC0           __REG(0x48000008)  /* Static Memory Control Register 0 
*/
+#define MSC1           __REG(0x4800000C)  /* Static Memory Control Register 1 
*/
+#define MSC2           __REG(0x48000010)  /* Static Memory Control Register 2 
*/
+#define MECR           __REG(0x48000014)  /* Expansion Memory (PCMCIA/Compact 
Flash) Bus Configuration */
+#define SXLCR          __REG(0x48000018)  /* LCR value to be written to 
SDRAM-Timing Synchronous Flash */
+#define SXCNFG         __REG(0x4800001C)  /* Synchronous Static Memory Control 
Register */
+#define SXMRS          __REG(0x48000024)  /* MRS value to be written to 
Synchronous Flash or SMROM */
+#define MCMEM0         __REG(0x48000028)  /* Card interface Common Memory 
Space Socket 0 Timing */
+#define MCMEM1         __REG(0x4800002C)  /* Card interface Common Memory 
Space Socket 1 Timing */
+#define MCATT0         __REG(0x48000030)  /* Card interface Attribute Space 
Socket 0 Timing Configuration */
+#define MCATT1         __REG(0x48000034)  /* Card interface Attribute Space 
Socket 1 Timing Configuration */
+#define MCIO0          __REG(0x48000038)  /* Card interface I/O Space Socket 0 
Timing Configuration */
+#define MCIO1          __REG(0x4800003C)  /* Card interface I/O Space Socket 1 
Timing Configuration */
+#define MDMRS          __REG(0x48000040)  /* MRS value to be written to SDRAM 
*/
+#define BOOT_DEF       __REG(0x48000044)  /* Read-Only Boot-Time Register. 
Contains BOOT_SEL and PKG_SEL */
+
+/*
+ * More handy macros for PCMCIA
+ *
+ * Arg is socket number
+ */
+#define MCMEM(s)       __REG2(0x48000028, (s)<<2 )  /* Card interface Common 
Memory Space Socket s Timing */
+#define MCATT(s)       __REG2(0x48000030, (s)<<2 )  /* Card interface 
Attribute Space Socket s Timing Configuration */
+#define MCIO(s)                __REG2(0x48000038, (s)<<2 )  /* Card interface 
I/O Space Socket s Timing Configuration */
+
+/* MECR register defines */
+#define MECR_NOS       (1 << 0)        /* Number Of Sockets: 0 -> 1 sock, 1 -> 
2 sock */
+#define MECR_CIT       (1 << 1)        /* Card Is There: 0 -> no card, 1 -> 
card inserted */
+
+#define MDREFR_K0DB4   (1 << 29)       /* SDCLK0 Divide by 4 Control/Status */
+#define MDREFR_K2FREE  (1 << 25)       /* SDRAM Free-Running Control */
+#define MDREFR_K1FREE  (1 << 24)       /* SDRAM Free-Running Control */
+#define MDREFR_K0FREE  (1 << 23)       /* SDRAM Free-Running Control */
+#define MDREFR_SLFRSH  (1 << 22)       /* SDRAM Self-Refresh Control/Status */
+#define MDREFR_APD     (1 << 20)       /* SDRAM/SSRAM Auto-Power-Down Enable */
+#define MDREFR_K2DB2   (1 << 19)       /* SDCLK2 Divide by 2 Control/Status */
+#define MDREFR_K2RUN   (1 << 18)       /* SDCLK2 Run Control/Status */
+#define MDREFR_K1DB2   (1 << 17)       /* SDCLK1 Divide by 2 Control/Status */
+#define MDREFR_K1RUN   (1 << 16)       /* SDCLK1 Run Control/Status */
+#define MDREFR_E1PIN   (1 << 15)       /* SDCKE1 Level Control/Status */
+#define MDREFR_K0DB2   (1 << 14)       /* SDCLK0 Divide by 2 Control/Status */
+#define MDREFR_K0RUN   (1 << 13)       /* SDCLK0 Run Control/Status */
+#define MDREFR_E0PIN   (1 << 12)       /* SDCKE0 Level Control/Status */
+
+
+#ifdef CONFIG_PXA27x
+
+#define ARB_CNTRL      __REG(0x48000048)  /* Arbiter Control Register */
+
+#define ARB_DMA_SLV_PARK       (1<<31)    /* Be parked with DMA slave when 
idle */
+#define ARB_CI_PARK            (1<<30)    /* Be parked with Camera Interface 
when idle */
+#define ARB_EX_MEM_PARK        (1<<29)    /* Be parked with external MEMC when 
idle */
+#define ARB_INT_MEM_PARK       (1<<28)    /* Be parked with internal MEMC when 
idle */
+#define ARB_USB_PARK           (1<<27)    /* Be parked with USB when idle */
+#define ARB_LCD_PARK           (1<<26)    /* Be parked with LCD when idle */
+#define ARB_DMA_PARK           (1<<25)    /* Be parked with DMA when idle */
+#define ARB_CORE_PARK          (1<<24)    /* Be parked with core when idle */
+#define ARB_LOCK_FLAG          (1<<23)    /* Only Locking masters gain access 
to the bus */
+
+#endif
+
+#endif
-
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