Gitweb:     
http://git.kernel.org/git/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commit;h=d752542ade337f059d12c59c4bc9c312befa1f1e
Commit:     d752542ade337f059d12c59c4bc9c312befa1f1e
Parent:     a096a7e4762f685364df5ca03394eb63bbdb93df
Author:     Paul Mundt <[EMAIL PROTECTED]>
AuthorDate: Thu Nov 8 19:00:27 2007 +0900
Committer:  Paul Mundt <[EMAIL PROTECTED]>
CommitDate: Mon Jan 28 13:18:39 2008 +0900

    sh: Add cache definitions for SH-5.
    
    Signed-off-by: Paul Mundt <[EMAIL PROTECTED]>
---
 include/asm-sh/cpu-sh5/cache.h |   94 +++++++++++++++++++++++++++
 include/asm-sh64/cache.h       |  139 ----------------------------------------
 2 files changed, 94 insertions(+), 139 deletions(-)

diff --git a/include/asm-sh/cpu-sh5/cache.h b/include/asm-sh/cpu-sh5/cache.h
new file mode 100644
index 0000000..2d1f9c2
--- /dev/null
+++ b/include/asm-sh/cpu-sh5/cache.h
@@ -0,0 +1,94 @@
+#ifndef __ASM_SH64_CACHE_H
+#define __ASM_SH64_CACHE_H
+
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * include/asm-sh64/cache.h
+ *
+ * Copyright (C) 2000, 2001  Paolo Alberelli
+ * Copyright (C) 2003, 2004  Paul Mundt
+ *
+ */
+
+#define L1_CACHE_SHIFT         5
+
+/* Valid and Dirty bits */
+#define SH_CACHE_VALID         (1LL<<0)
+#define SH_CACHE_UPDATED       (1LL<<57)
+
+/* Cache flags */
+#define SH_CACHE_MODE_WT       (1LL<<0)
+#define SH_CACHE_MODE_WB       (1LL<<1)
+
+/*
+ * Control Registers.
+ */
+#define ICCR_BASE      0x01600000      /* Instruction Cache Control Register */
+#define ICCR_REG0      0               /* Register 0 offset */
+#define ICCR_REG1      1               /* Register 1 offset */
+#define ICCR0          ICCR_BASE+ICCR_REG0
+#define ICCR1          ICCR_BASE+ICCR_REG1
+
+#define ICCR0_OFF      0x0             /* Set ICACHE off */
+#define ICCR0_ON       0x1             /* Set ICACHE on */
+#define ICCR0_ICI      0x2             /* Invalidate all in IC */
+
+#define ICCR1_NOLOCK   0x0             /* Set No Locking */
+
+#define OCCR_BASE      0x01E00000      /* Operand Cache Control Register */
+#define OCCR_REG0      0               /* Register 0 offset */
+#define OCCR_REG1      1               /* Register 1 offset */
+#define OCCR0          OCCR_BASE+OCCR_REG0
+#define OCCR1          OCCR_BASE+OCCR_REG1
+
+#define OCCR0_OFF      0x0             /* Set OCACHE off */
+#define OCCR0_ON       0x1             /* Set OCACHE on */
+#define OCCR0_OCI      0x2             /* Invalidate all in OC */
+#define OCCR0_WT       0x4             /* Set OCACHE in WT Mode */
+#define OCCR0_WB       0x0             /* Set OCACHE in WB Mode */
+
+#define OCCR1_NOLOCK   0x0             /* Set No Locking */
+
+/*
+ * SH-5
+ * A bit of description here, for neff=32.
+ *
+ *                               |<--- tag  (19 bits) --->|
+ * +-----------------------------+-----------------+------+----------+------+
+ * |                             |                 | ways |set index |offset|
+ * +-----------------------------+-----------------+------+----------+------+
+ *                                ^                 2 bits   8 bits   5 bits
+ *                                +- Bit 31
+ *
+ * Cacheline size is based on offset: 5 bits = 32 bytes per line
+ * A cache line is identified by a tag + set but OCACHETAG/ICACHETAG
+ * have a broader space for registers. These are outlined by
+ * CACHE_?C_*_STEP below.
+ *
+ */
+
+/* Instruction cache */
+#define CACHE_IC_ADDRESS_ARRAY 0x01000000
+
+/* Operand Cache */
+#define CACHE_OC_ADDRESS_ARRAY 0x01800000
+
+/* These declarations relate to cache 'synonyms' in the operand cache.  A
+   'synonym' occurs where effective address bits overlap between those used for
+   indexing the cache sets and those passed to the MMU for translation.  In the
+   case of SH5-101 & SH5-103, only bit 12 is affected for 4k pages. */
+
+#define CACHE_OC_N_SYNBITS  1               /* Number of synonym bits */
+#define CACHE_OC_SYN_SHIFT  12
+/* Mask to select synonym bit(s) */
+#define CACHE_OC_SYN_MASK   (((1UL<<CACHE_OC_N_SYNBITS)-1)<<CACHE_OC_SYN_SHIFT)
+
+/*
+ * Instruction cache can't be invalidated based on physical addresses.
+ * No Instruction Cache defines required, then.
+ */
+
+#endif /* __ASM_SH64_CACHE_H */
diff --git a/include/asm-sh64/cache.h b/include/asm-sh64/cache.h
deleted file mode 100644
index a4f36f0..0000000
--- a/include/asm-sh64/cache.h
+++ /dev/null
@@ -1,139 +0,0 @@
-#ifndef __ASM_SH64_CACHE_H
-#define __ASM_SH64_CACHE_H
-
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * include/asm-sh64/cache.h
- *
- * Copyright (C) 2000, 2001  Paolo Alberelli
- * Copyright (C) 2003, 2004  Paul Mundt
- *
- */
-#include <asm/cacheflush.h>
-
-#define L1_CACHE_SHIFT         5
-/* bytes per L1 cache line */
-#define L1_CACHE_BYTES         (1 << L1_CACHE_SHIFT)
-#define L1_CACHE_ALIGN_MASK    (~(L1_CACHE_BYTES - 1))
-#define L1_CACHE_ALIGN(x)      (((x)+(L1_CACHE_BYTES - 1)) & 
L1_CACHE_ALIGN_MASK)
-#define L1_CACHE_SIZE_BYTES    (L1_CACHE_BYTES << 10)
-
-#ifdef MODULE
-#define __cacheline_aligned __attribute__((__aligned__(L1_CACHE_BYTES)))
-#else
-#define __cacheline_aligned                                    \
-  __attribute__((__aligned__(L1_CACHE_BYTES),                  \
-                __section__(".data.cacheline_aligned")))
-#endif
-
-/*
- * Control Registers.
- */
-#define ICCR_BASE      0x01600000      /* Instruction Cache Control Register */
-#define ICCR_REG0      0               /* Register 0 offset */
-#define ICCR_REG1      1               /* Register 1 offset */
-#define ICCR0          ICCR_BASE+ICCR_REG0
-#define ICCR1          ICCR_BASE+ICCR_REG1
-
-#define ICCR0_OFF      0x0             /* Set ICACHE off */
-#define ICCR0_ON       0x1             /* Set ICACHE on */
-#define ICCR0_ICI      0x2             /* Invalidate all in IC */
-
-#define ICCR1_NOLOCK   0x0             /* Set No Locking */
-
-#define OCCR_BASE      0x01E00000      /* Operand Cache Control Register */
-#define OCCR_REG0      0               /* Register 0 offset */
-#define OCCR_REG1      1               /* Register 1 offset */
-#define OCCR0          OCCR_BASE+OCCR_REG0
-#define OCCR1          OCCR_BASE+OCCR_REG1
-
-#define OCCR0_OFF      0x0             /* Set OCACHE off */
-#define OCCR0_ON       0x1             /* Set OCACHE on */
-#define OCCR0_OCI      0x2             /* Invalidate all in OC */
-#define OCCR0_WT       0x4             /* Set OCACHE in WT Mode */
-#define OCCR0_WB       0x0             /* Set OCACHE in WB Mode */
-
-#define OCCR1_NOLOCK   0x0             /* Set No Locking */
-
-
-/*
- * SH-5
- * A bit of description here, for neff=32.
- *
- *                               |<--- tag  (19 bits) --->|
- * +-----------------------------+-----------------+------+----------+------+
- * |                             |                 | ways |set index |offset|
- * +-----------------------------+-----------------+------+----------+------+
- *                                ^                 2 bits   8 bits   5 bits
- *                                +- Bit 31
- *
- * Cacheline size is based on offset: 5 bits = 32 bytes per line
- * A cache line is identified by a tag + set but OCACHETAG/ICACHETAG
- * have a broader space for registers. These are outlined by
- * CACHE_?C_*_STEP below.
- *
- */
-
-/* Valid and Dirty bits */
-#define SH_CACHE_VALID         (1LL<<0)
-#define SH_CACHE_UPDATED       (1LL<<57)
-
-/* Cache flags */
-#define SH_CACHE_MODE_WT       (1LL<<0)
-#define SH_CACHE_MODE_WB       (1LL<<1)
-
-#ifndef __ASSEMBLY__
-
-/*
- * Cache information structure.
- *
- * Defined for both I and D cache, per-processor.
- */
-struct cache_info {
-       unsigned int ways;
-       unsigned int sets;
-       unsigned int linesz;
-
-       unsigned int way_shift;
-       unsigned int entry_shift;
-       unsigned int set_shift;
-       unsigned int way_step_shift;
-       unsigned int asid_shift;
-
-       unsigned int way_ofs;
-
-       unsigned int asid_mask;
-       unsigned int idx_mask;
-       unsigned int epn_mask;
-
-       unsigned long flags;
-};
-
-#endif /* __ASSEMBLY__ */
-
-/* Instruction cache */
-#define CACHE_IC_ADDRESS_ARRAY 0x01000000
-
-/* Operand Cache */
-#define CACHE_OC_ADDRESS_ARRAY 0x01800000
-
-/* These declarations relate to cache 'synonyms' in the operand cache.  A
-   'synonym' occurs where effective address bits overlap between those used for
-   indexing the cache sets and those passed to the MMU for translation.  In the
-   case of SH5-101 & SH5-103, only bit 12 is affected for 4k pages. */
-
-#define CACHE_OC_N_SYNBITS  1               /* Number of synonym bits */
-#define CACHE_OC_SYN_SHIFT  12
-/* Mask to select synonym bit(s) */
-#define CACHE_OC_SYN_MASK   (((1UL<<CACHE_OC_N_SYNBITS)-1)<<CACHE_OC_SYN_SHIFT)
-
-
-/*
- * Instruction cache can't be invalidated based on physical addresses.
- * No Instruction Cache defines required, then.
- */
-
-#endif /* __ASM_SH64_CACHE_H */
-
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