Commit:     c7c6b39050aed4af913c17970ebfb592bae757fc
Parent:     930bff882296c02ca81db108672ef4ca06c37db5
Author:     Thomas Bogendoerfer <[EMAIL PROTECTED]>
AuthorDate: Tue Nov 27 19:31:33 2007 +0100
Committer:  Ralf Baechle <[EMAIL PROTECTED]>
CommitDate: Tue Jan 29 10:14:58 2008 +0000

    [MIPS] Use correct dma flushing in dma_cache_sync()
    Not cache coherent R10k systems (like IP28) need to do real cache
    invalidates in dma_cache_sync().
    Signed-off-by: Thomas Bogendoerfer <[EMAIL PROTECTED]>
    Signed-off-by: Ralf Baechle <[EMAIL PROTECTED]>
 arch/mips/mm/dma-default.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/mips/mm/dma-default.c b/arch/mips/mm/dma-default.c
index 810535d..ae39dd8 100644
--- a/arch/mips/mm/dma-default.c
+++ b/arch/mips/mm/dma-default.c
@@ -383,7 +383,7 @@ void dma_cache_sync(struct device *dev, void *vaddr, size_t 
        BUG_ON(direction == DMA_NONE);
        if (!plat_device_is_coherent(dev))
-               dma_cache_wback_inv((unsigned long)vaddr, size);
+               __dma_sync((unsigned long)vaddr, size, direction);
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